def __init__(self, phy, clk_freq, with_crc=True): rx_pipeline = [phy] tx_pipeline = [phy] # depacketizer / packetizer self.submodules.depacketizer = LiteUSBDepacketizer(clk_freq) self.submodules.packetizer = LiteUSBPacketizer() rx_pipeline += [self.depacketizer] tx_pipeline += [self.packetizer] if with_crc: # crc checker / inserter self.submodules.crc_rx = LiteUSBCRC32Checker() self.submodules.crc_tx = LiteUSBCRC32Inserter() rx_pipeline += [self.crc_rx] tx_pipeline += [self.crc_tx] # crossbar self.submodules.crossbar = LiteUSBCrossbar() rx_pipeline += [self.crossbar.master] tx_pipeline += [self.crossbar.master] # graph self.submodules.rx_pipeline = stream.Pipeline(*rx_pipeline) self.submodules.tx_pipeline = stream.Pipeline(*reversed(tx_pipeline))
def __init__(self, port_from, port_to, reverse=False): assert port_from.clock_domain == port_to.clock_domain assert port_from.data_width > port_to.data_width assert port_from.mode == port_to.mode if port_from.data_width % port_to.data_width: raise ValueError("Ratio must be an int") # # # ratio = port_from.data_width//port_to.data_width mode = port_from.mode counter = Signal(max=ratio) counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", counter_reset.eq(1), If(port_from.cmd.valid, NextState("CONVERT") ) ) fsm.act("CONVERT", port_to.cmd.valid.eq(1), port_to.cmd.we.eq(port_from.cmd.we), port_to.cmd.addr.eq(port_from.cmd.addr*ratio + counter), If(port_to.cmd.ready, counter_ce.eq(1), If(counter == ratio - 1, port_from.cmd.ready.eq(1), NextState("IDLE") ) ) ) if mode == "write" or mode == "both": wdata_converter = stream.StrideConverter( port_from.wdata.description, port_to.wdata.description, reverse=reverse) self.submodules += wdata_converter self.submodules += stream.Pipeline( port_from.wdata, wdata_converter, port_to.wdata) if mode == "read" or mode == "both": rdata_converter = stream.StrideConverter( port_to.rdata.description, port_from.rdata.description, reverse=reverse) self.submodules += rdata_converter self.submodules += stream.Pipeline( port_to.rdata, rdata_converter, port_from.rdata)
def __init__(self, port_from, port_to, cmd_depth=4, wdata_depth=16, rdata_depth=16): assert port_from.address_width == port_to.address_width assert port_from.data_width == port_to.data_width assert port_from.mode == port_to.mode address_width = port_from.address_width data_width = port_from.data_width mode = port_from.mode clock_domain_from = port_from.clock_domain clock_domain_to = port_to.clock_domain # # # cmd_fifo = stream.AsyncFIFO([("we", 1), ("addr", address_width)], cmd_depth) cmd_fifo = ClockDomainsRenamer({ "write": clock_domain_from, "read": clock_domain_to })(cmd_fifo) self.submodules += cmd_fifo self.submodules += stream.Pipeline(port_from.cmd, cmd_fifo, port_to.cmd) if mode == "write" or mode == "both": wdata_fifo = stream.AsyncFIFO([("data", data_width), ("we", data_width // 8)], wdata_depth) wdata_fifo = ClockDomainsRenamer({ "write": clock_domain_from, "read": clock_domain_to })(wdata_fifo) self.submodules += wdata_fifo self.submodules += stream.Pipeline(port_from.wdata, wdata_fifo, port_to.wdata) if mode == "read" or mode == "both": rdata_fifo = stream.AsyncFIFO([("data", data_width)], rdata_depth) rdata_fifo = ClockDomainsRenamer({ "write": clock_domain_to, "read": clock_domain_from })(rdata_fifo) self.submodules += rdata_fifo self.submodules += stream.Pipeline(port_to.rdata, rdata_fifo, port_from.rdata)
def __init__(self, port_from, port_to, reverse=False): assert port_from.clock_domain == port_to.clock_domain assert port_from.data_width > port_to.data_width assert port_from.mode == port_to.mode if port_from.data_width % port_to.data_width: raise ValueError("Ratio must be an int") # # # ratio = port_from.data_width//port_to.data_width mode = port_from.mode count = Signal(max=ratio) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", NextValue(count, 0), If(port_from.cmd.valid, NextState("CONVERT") ) ) fsm.act("CONVERT", port_to.cmd.valid.eq(1), port_to.cmd.we.eq(port_from.cmd.we), port_to.cmd.addr.eq(port_from.cmd.addr*ratio + count), If(port_to.cmd.ready, NextValue(count, count + 1), If(count == (ratio - 1), port_from.cmd.ready.eq(1), NextState("IDLE") ) ) ) if mode in ["write", "both"]: wdata_converter = stream.StrideConverter( description_from = port_from.wdata.description, description_to = port_to.wdata.description, reverse = reverse) self.submodules += wdata_converter self.submodules += stream.Pipeline(port_from.wdata, wdata_converter, port_to.wdata) if mode in ["read", "both"]: rdata_converter = stream.StrideConverter( description_from = port_to.rdata.description, description_to = port_from.rdata.description, reverse = reverse) self.submodules += rdata_converter self.submodules += stream.Pipeline( port_to.rdata, rdata_converter, port_from.rdata)
def __init__(self, with_converter=False): self.submodules.host = Host(64, root_id, endpoint_id, phy_debug=False, chipset_debug=False, chipset_split=True, chipset_reordering=True, host_debug=True) self.submodules.endpoint = LitePCIeEndpoint(self.host.phy, max_pending_requests=8, with_reordering=True) self.submodules.dma_reader = LitePCIeDMAReader(self.endpoint, self.endpoint.crossbar.get_master_port(read_only=True)) self.submodules.dma_writer = LitePCIeDMAWriter(self.endpoint, self.endpoint.crossbar.get_master_port(write_only=True)) if with_converter: self.submodules.up_converter = stream.StrideConverter(dma_layout(16), dma_layout(64)) self.submodules.down_converter = stream.StrideConverter(dma_layout(64), dma_layout(16)) self.submodules += stream.Pipeline(self.dma_reader, self.down_converter, self.up_converter, self.dma_writer) else: self.comb += self.dma_reader.source.connect(self.dma_writer.sink) self.submodules.msi = LitePCIeMSI(2) self.comb += [ self.msi.irqs[log2_int(DMA_READER_IRQ)].eq(self.dma_reader.irq), self.msi.irqs[log2_int(DMA_WRITER_IRQ)].eq(self.dma_writer.irq) ] self.submodules.irq_handler = InterruptHandler(debug=False) self.comb += self.msi.source.connect(self.irq_handler.sink)
def __init__(self, groups, depth, clock_domain="sys", trigger_depth=16, csr_csv=None): self.groups = groups = self.format_groups(groups) self.depth = depth self.data_width = data_width = max([sum([len(s) for s in g]) for g in groups.values()]) self.csr_csv = csr_csv # # # # Create scope clock domain self.clock_domains.cd_scope = ClockDomain() self.comb += self.cd_scope.clk.eq(ClockSignal(clock_domain)) # Mux self.submodules.mux = _Mux(data_width, len(groups)) for i, signals in groups.items(): self.comb += [ self.mux.sinks[i].valid.eq(1), self.mux.sinks[i].data.eq(Cat(signals)) ] # Frontend self.submodules.trigger = _Trigger(data_width, depth=trigger_depth) self.submodules.subsampler = _SubSampler(data_width) # Storage self.submodules.storage = _Storage(data_width, depth) # Pipeline self.submodules.pipeline = stream.Pipeline( self.mux.source, self.trigger, self.subsampler, self.storage.sink)
def __init__(self, port_from, port_to, cmd_depth=4, wdata_depth=16, rdata_depth=16): assert port_from.aw == port_to.aw assert port_from.dw == port_to.dw assert port_from.mode == port_to.mode aw = port_from.aw dw = port_from.dw mode = port_from.mode cd_from = port_from.cd cd_to = port_to.cd # # # cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], cmd_depth) cmd_fifo = ClockDomainsRenamer({ "write": cd_from, "read": cd_to })(cmd_fifo) self.submodules += cmd_fifo self.submodules += stream.Pipeline(port_from.cmd, cmd_fifo, port_to.cmd) if mode == "write" or mode == "both": wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw // 8)], wdata_depth) wdata_fifo = ClockDomainsRenamer({ "write": cd_from, "read": cd_to })(wdata_fifo) self.submodules += wdata_fifo self.submodules += stream.Pipeline(port_from.wdata, wdata_fifo, port_to.wdata) if mode == "read" or mode == "both": rdata_fifo = stream.AsyncFIFO([("data", dw)], rdata_depth) rdata_fifo = ClockDomainsRenamer({ "write": cd_to, "read": cd_from })(rdata_fifo) self.submodules += rdata_fifo self.submodules += stream.Pipeline(port_to.rdata, rdata_fifo, port_from.rdata)
def __init__(self, phy, clk_freq): rx_pipeline = [phy] tx_pipeline = [phy] # depacketizer / packetizer self.submodules.depacketizer = USBDepacketizer(clk_freq) self.submodules.packetizer = USBPacketizer() rx_pipeline += [self.depacketizer] tx_pipeline += [self.packetizer] # crossbar self.submodules.crossbar = USBCrossbar() rx_pipeline += [self.crossbar.master] tx_pipeline += [self.crossbar.master] # graph self.submodules.rx_pipeline = stream.Pipeline(*rx_pipeline) self.submodules.tx_pipeline = stream.Pipeline(*reversed(tx_pipeline))
def __init__(self, port_from, port_to, cmd_depth=4, wdata_depth=16, rdata_depth=16): assert port_from.address_width == port_to.address_width assert port_from.data_width == port_to.data_width assert port_from.mode == port_to.mode address_width = port_from.address_width data_width = port_from.data_width mode = port_from.mode # # # cmd_cdc = stream.ClockDomainCrossing(layout=[("we", 1), ("addr", address_width)], cd_from=port_from.clock_domain, cd_to=port_to.clock_domain, depth=cmd_depth) self.submodules += cmd_cdc self.submodules += stream.Pipeline(port_from.cmd, cmd_cdc, port_to.cmd) if mode in ["write", "both"]: wdata_cdc = stream.ClockDomainCrossing( layout=[("data", data_width), ("we", data_width // 8)], cd_from=port_from.clock_domain, cd_to=port_to.clock_domain, depth=wdata_depth) self.submodules += wdata_cdc self.submodules += stream.Pipeline(port_from.wdata, wdata_cdc, port_to.wdata) if mode in ["read", "both"]: rdata_cdc = stream.ClockDomainCrossing( layout=[("data", data_width)], cd_from=port_to.clock_domain, cd_to=port_from.clock_domain, depth=rdata_depth) self.submodules += rdata_cdc self.submodules += stream.Pipeline(port_to.rdata, rdata_cdc, port_from.rdata)
def __init__(self, clk_freq): self.sink = sink = stream.Endpoint(phy_description(32)) self.source = source = stream.Endpoint(phy_description(32)) # # # rx_pipeline = [sink] tx_pipeline = [source] # depacketizer / packetizer self.submodules.depacketizer = Depacketizer(clk_freq) self.submodules.packetizer = Packetizer() rx_pipeline += [self.depacketizer] tx_pipeline += [self.packetizer] # crossbar self.submodules.crossbar = Crossbar() rx_pipeline += [self.crossbar.master] tx_pipeline += [self.crossbar.master] # graph self.submodules.rx_pipeline = stream.Pipeline(*rx_pipeline) self.submodules.tx_pipeline = stream.Pipeline(*reversed(tx_pipeline))
def __init__(self, groups, depth, clock_domain="sys", trigger_depth=16, **kwargs): # retro-compatibility # FIXME: remove if "cd" in kwargs: print( "[WARNING] Please update LiteScopeAnalyzer's \"cd\" parameter to \"clock_domain\"" ) clock_domain = kwargs["cd"] self.groups = groups = self.format_groups(groups) self.depth = depth self.data_width = data_width = max( [sum([len(s) for s in g]) for g in groups.values()]) # # # # create scope clock domain self.clock_domains.cd_scope = ClockDomain() self.comb += [ self.cd_scope.clk.eq(ClockSignal(clock_domain)), self.cd_scope.rst.eq(ResetSignal(clock_domain)) ] # mux self.submodules.mux = _Mux(data_width, len(groups)) for i, signals in groups.items(): self.comb += [ self.mux.sinks[i].valid.eq(1), self.mux.sinks[i].data.eq(Cat(signals)) ] # frontend self.submodules.trigger = _Trigger(data_width, depth=trigger_depth) self.submodules.subsampler = _SubSampler(data_width) # storage self.submodules.storage = _Storage(data_width, depth) # pipeline self.submodules.pipeline = stream.Pipeline(self.mux.source, self.trigger, self.subsampler, self.storage.sink)
def __init__(self, port_from, port_to, reverse=False): assert port_from.clock_domain == port_to.clock_domain assert port_from.data_width < port_to.data_width assert port_from.mode == port_to.mode assert port_from.mode == "write" if port_to.data_width % port_from.data_width: raise ValueError("Ratio must be an int") # # # ratio = port_to.data_width // port_from.data_width we = Signal() address = Signal(port_to.address_width) counter = Signal(max=ratio) counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act( "IDLE", port_from.cmd.ready.eq(1), If(port_from.cmd.valid, counter_ce.eq(1), NextValue(we, port_from.cmd.we), NextValue(address, port_from.cmd.addr), NextState("RECEIVE"))) fsm.act( "RECEIVE", port_from.cmd.ready.eq(1), If(port_from.cmd.valid, counter_ce.eq(1), If(counter == ratio - 1, NextState("GENERATE")))) fsm.act("GENERATE", port_to.cmd.valid.eq(1), port_to.cmd.we.eq(we), port_to.cmd.addr.eq(address[log2_int(ratio):]), If(port_to.cmd.ready, NextState("IDLE"))) wdata_converter = stream.StrideConverter(port_from.wdata.description, port_to.wdata.description, reverse=reverse) self.submodules += wdata_converter self.submodules += stream.Pipeline(port_from.wdata, wdata_converter, port_to.wdata)
def __init__(self, dw, cd_ratio): self.sink = stream.Endpoint(core_layout(dw)) self.source = stream.Endpoint(core_layout(dw * cd_ratio)) # # # self.submodules.buffer = stream.Buffer(core_layout(dw)) self.submodules.trigger = FrontendTrigger(dw) self.submodules.subsampler = FrontendSubSampler(dw) self.submodules.converter = stream.StrideConverter( core_layout(dw, 1), core_layout(dw * cd_ratio, cd_ratio)) self.submodules.fifo = ClockDomainsRenamer({ "write": "sys", "read": "new_sys" })(stream.AsyncFIFO(core_layout(dw * cd_ratio, cd_ratio), 8)) self.submodules.pipeline = stream.Pipeline(self.sink, self.buffer, self.trigger, self.subsampler, self.converter, self.fifo, self.source)