Example #1
0
#!/usr/bin/env python3

import sys
sys.path.insert(0, '/opt')

from litex.soc.tools.remote import RemoteClient

wb = RemoteClient()
wb.open()

# # #

# get identifier
fpga_id = ""
for i in range(256):
    c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff)
    fpga_id += c
    if c == "\0":
        break
print("fpga_id: " + fpga_id)

# # #

wb.close()
Example #2
0
    if wb_amc.regs.serwb_phy_control_scrambling_enable.read():
        print("Disabling scrambling")
        wb_rtm.regs.serwb_phy_control_scrambling_enable.write(0)
        wb_amc.regs.serwb_phy_control_scrambling_enable.write(0)
    else:
        print("Enabling scrambling")
        wb_rtm.regs.serwb_phy_control_scrambling_enable.write(1)
        wb_amc.regs.serwb_phy_control_scrambling_enable.write(1)

elif sys.argv[1] == "wishbone":
    write_pattern(128)
    errors = check_pattern(128, debug=True)
    print("errors: {:d}".format(errors))
elif sys.argv[1] == "dump":
    for i in range(32):
        print("{:08x}".format(wb_amc.read(wb_amc.mems.serwb.base + 4 * i)))
elif sys.argv[1] == "analyzer_rtm":
    analyzer = LiteScopeAnalyzerDriver(wb_rtm.regs,
                                       "analyzer",
                                       config_csv="../sayma_rtm/analyzer.csv",
                                       debug=True)
    analyzer.configure_trigger(cond={"soc_activity": 1})
    analyzer.run(offset=32, length=128)

    time.sleep(1)
    #wb_amc.regs.serwb_test_do_write.write(1)
    wb_amc.regs.serwb_test_do_read.write(1)

    analyzer.wait_done()
    analyzer.upload()
    analyzer.save("dump.vcd")
Example #3
0
from litex.soc.tools.remote import RemoteClient

wb = RemoteClient()
wb.open()

# # #

identifier = ""
for i in range(30):
    identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))
print("link up   : {}".format(wb.regs.pcie_phy_lnk_up.read()))
print("bus_master_enable : {}".format(wb.regs.pcie_phy_bus_master_enable.read()))
print("msi_enable : {}".format(wb.regs.pcie_phy_msi_enable.read()))
print("max_req_request_size : {}".format(wb.regs.pcie_phy_max_request_size.read()))
print("max_payload_size : {}".format(wb.regs.pcie_phy_max_payload_size.read()))

# # #

wb.close()
Example #4
0
from litex.soc.tools.remote import RemoteClient

wb = RemoteClient()
wb.open()

# # #

identifier = ""
for i in range(30):
    identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))

SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))

# # #

wb.close()
Example #5
0
#!/usr/bin/env python3
from litex.soc.tools.remote import RemoteClient

rom_base = 0x00000000
dump_size = 0x8000
words_per_packet = 128

wb = RemoteClient()
wb.open()

# # #

print("dumping cpu rom to dump.bin...")
dump = []
for n in range(dump_size // (words_per_packet * 4)):
    dump += wb.read(rom_base + n * words_per_packet * 4, words_per_packet)
f = open("dump.bin", "wb")
for v in dump:
    f.write(v.to_bytes(4, byteorder="big"))
f.close()

# # #

wb.close()
Example #6
0
#!/usr/bin/env python3
import time

from litex.soc.tools.remote import RemoteClient

wb = RemoteClient()
wb.open()

#print("trigger_mem_full: ")
#t = wb.read(0xe000b838)
#print(t)

print("Temperature: ")
t = wb.read(0xe0005800)
t <<= 8
t |= wb.read(0xe0005804)
print(t * 503.975 / 4096 - 273.15, "C")

print("VCCint: ")
t = wb.read(0xe0005808)
t <<= 8
t |= wb.read(0xe000580c)
print(t / 0x555, "V")

print("VCCaux: ")
t = wb.read(0xe0005810)
t <<= 8
t |= wb.read(0xe0005814)
print(t / 0x555, "V")

print("VCCbram: ")
Example #7
0
from litex.soc.tools.remote import RemoteClient

wb = RemoteClient()
wb.open()

# # #

identifier = ""
for i in range(30):
    identifier += chr(wb.read(wb.bases.identifier_mem + 4 *
                              (i + 1)))  # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency /
                                 1000000))

SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))

# # #

wb.close()
from litex.soc.tools.remote import RemoteClient

wb = RemoteClient()
wb.open()

# # #

identifier = ""
for i in range(30):
    identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))

# # #

wb.close()