class CrossoverUART: def __init__(self, host="localhost", base_address=0): # FIXME: add command line arguments self.bus = RemoteClient(host=host, base_address=base_address) def open(self): self.bus.open() self.file, self.name = pty.openpty() self.pty2crossover_thread = multiprocessing.Process(target=self.pty2crossover) self.crossover2pty_thread = multiprocessing.Process(target=self.crossover2pty) self.pty2crossover_thread.start() self.crossover2pty_thread.start() def close(self): self.bus.close() self.pty2crossover_thread.terminate() self.crossover2pty_thread.terminate() def pty2crossover(self): while True: r = os.read(self.file, 1) self.bus.regs.uart_xover_rxtx.write(ord(r)) def crossover2pty(self): while True: if self.bus.regs.uart_txfull.read(): length = 16 elif not self.bus.regs.uart_xover_rxempty.read(): length = 1 else: length = 0 if length: r = self.bus.read(self.bus.regs.uart_xover_rxtx.addr, length=length, burst="fixed") for v in r: os.write(self.file, bytes(chr(v).encode("utf-8")))
class BridgeUART: def __init__(self, name="uart_xover", host="localhost", base_address=None, csr_csv=None): self.bus = RemoteClient(host=host, base_address=base_address, csr_csv=csr_csv) present = False for k, v in self.bus.regs.d.items(): if f"{name}_" in k: setattr(self, k.replace(f"{name}_", ""), v) present = True if not present: raise ValueError(f"CrossoverUART {name} not present in design.") # FIXME: On PCIe designs, CSR is remapped to 0 to limit BAR0 size. if base_address is None and hasattr(self.bus.bases, "pcie_phy"): self.bus.base_address = -self.bus.mems.csr.base def open(self): self.bus.open() self.file, self.name = pty.openpty() self.pty2crossover_thread = multiprocessing.Process( target=self.pty2crossover) self.crossover2pty_thread = multiprocessing.Process( target=self.crossover2pty) self.pty2crossover_thread.start() self.crossover2pty_thread.start() def close(self): self.bus.close() self.pty2crossover_thread.terminate() self.crossover2pty_thread.terminate() def pty2crossover(self): while True: r = os.read(self.file, 1) self.rxtx.write(ord(r)) def crossover2pty(self): while True: if self.rxfull.read(): length = 16 elif not self.rxempty.read(): length = 1 else: time.sleep(1e-3) continue r = self.bus.read(self.rxtx.addr, length=length, burst="fixed") for v in r: os.write(self.file, bytes(chr(v).encode("utf-8")))
def ident_test(port): wb = RemoteClient(port=port) wb.open() fpga_identifier = "" for i in range(256): c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff) fpga_identifier += c if c == "\0": break print(fpga_identifier) wb.close()
class BridgeUART: def __init__(self, name="uart_xover", host="localhost", base_address=0): # FIXME: add command line arguments self.bus = RemoteClient(host=host, base_address=base_address) present = False for k, v in self.bus.regs.d.items(): if f"{name}_" in k: setattr(self, k.replace(f"{name}_", ""), v) present = True if not present: raise ValueError(f"CrossoverUART {name} not present in design.") def open(self): self.bus.open() self.file, self.name = pty.openpty() self.pty2crossover_thread = multiprocessing.Process( target=self.pty2crossover) self.crossover2pty_thread = multiprocessing.Process( target=self.crossover2pty) self.pty2crossover_thread.start() self.crossover2pty_thread.start() def close(self): self.bus.close() self.pty2crossover_thread.terminate() self.crossover2pty_thread.terminate() def pty2crossover(self): while True: r = os.read(self.file, 1) self.rxtx.write(ord(r)) def crossover2pty(self): while True: if self.rxfull.read(): length = 16 elif not self.rxempty.read(): length = 1 else: time.sleep(1e-3) continue r = self.bus.read(self.rxtx.addr, length=length, burst="fixed") for v in r: os.write(self.file, bytes(chr(v).encode("utf-8")))
# This file is Copyright (c) 2015-2018 Florent Kermarrec <*****@*****.**> # License: BSD from litex import RemoteClient wb = RemoteClient() wb.open() # # # identifier = "" for i in range(30): identifier += chr(wb.read(wb.bases.identifier_mem + 4 * (i + 1))) # TODO: why + 1? print(identifier) print("frequency : {}MHz".format(wb.constants.system_clock_frequency / 1000000)) SRAM_BASE = 0x02000000 wb.write(SRAM_BASE, [i for i in range(64)]) print(wb.read(SRAM_BASE, 64)) # # # wb.close()
from litex import RemoteClient wb = RemoteClient() wb.open() # # # fpga_id = "" for i in range(256): c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff) fpga_id += c if c == "\0": break print("fpga_id: " + fpga_id) print("frequency: {}MHz".format(wb.constants.system_clock_frequency / 1000000)) print("link up: {}".format(wb.regs.pcie_phy_lnk_up.read())) print("bus_master_enable: {}".format( wb.regs.pcie_phy_bus_master_enable.read())) print("msi_enable: {}".format(wb.regs.pcie_phy_msi_enable.read())) print("max_req_request_size: {}".format( wb.regs.pcie_phy_max_request_size.read())) print("max_payload_size: {}".format(wb.regs.pcie_phy_max_payload_size.read())) # # # wb.close()
self._length.write(length) self._start.write(1) print("Waiting...") while self._done.read() != 1: pass print("Done...") def upload(self, base, length): print("Upload of {} bytes to @0x{:08x}...".format(length, base)) datas = [] for i in range(length//4): datas.append(wb.read(base + 4*i)) return datas wb.write(wb.mems.main_ram.base, 0x11223344) test = wb.read(wb.mems.main_ram.base) print("----------" + str(test)) rx_recorder = DMARecorder("rx_dma_recorder") rx_recorder.capture(0x0000, 128) datas = rx_recorder.upload(wb.mems.main_ram.base, 128) for data in datas: print("{:08x}".format(data)) #tx_recorder = DMARecorder("tx_dma_recorder") #tx_recorder.capture(0x0000, 4 * 128) #datas = tx_recorder.upload(wb.mems.main_ram.base, 32) #for data in datas: # print("{:08x}".format(data)) # # #
length = 25 result = np.empty((0, length * 20)) wb = RemoteClient() wb.open() wb.debug = True for v in range(0x3800, 0x3FFF, 1): assert v >= 0x3000 assert v <= 0x3FFF wb.regs.spidac_mosi.write(v) wb.regs.spidac_control.write(0x1001) wb.regs.daq_trigger.write(0) wb.regs.daq_trigger.write(1) mem = wb.read(wb.mems.daq_memory.base, length=length) mem = np.array(mem) mem = np.fliplr(vec_bin_array(mem, 20)) mem = np.reshape(mem, (1, length * 20)) result = np.append(result, mem, axis=0) plt.matshow(result, origin='lower', aspect='auto') plt.show() np.save("data", result) [...] wb.close()
master_serdes_rx_bitslip = 17 slave_serdes_rx_bitslip = 9 prbs_test = False prbs_pattern = 0b01 prbs_loop = True analyzer_test = True # # # # get identifier identifier = "" for i in range(30): identifier += chr(wb.read(wb.bases.identifier_mem + 4*i)) print(identifier) # configure master wb.regs.master_serdes_control_rx_bitslip_value.write(master_serdes_rx_bitslip) # configure slave wb.regs.slave_serdes_control_rx_bitslip_value.write(slave_serdes_rx_bitslip) # prbs wb.regs.master_serdes_control_tx_prbs_config.write(0) wb.regs.master_serdes_control_rx_prbs_config.write(0) wb.regs.slave_serdes_control_tx_prbs_config.write(0)
def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=40): import time from litex import RemoteClient bus = RemoteClient() bus.open() # # # # Load BIOS and reboot SoC ctrl = BenchController(bus) ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds. ctrl.reboot() # PLL/ClkReg uspll = USPLL(bus) clkout0_clkreg1 = ClkReg1(uspll.read(0x8)) # Run calibration from freq_min to freq_max and log BIOS output. print("-" * 80) print( "Running calibration; sys_clk from {:3.3f}MHz to {:3.2f}MHz (step: {:3.2f}MHz)" .format(freq_min / 1e6, freq_max / 1e6, freq_step / 1e6)) print("-" * 80) print("") tested_vco_divs = [] for clk_freq in range(int(freq_min), int(freq_max), int(freq_step)): # Compute VCO divider, skip if already tested. vco_div = int(vco_freq / clk_freq) if vco_div in tested_vco_divs: continue tested_vco_divs.append(vco_div) print("-" * 40) print("sys_clk = {}MHz...".format(vco_freq / vco_div / 1e6)) print("-" * 40) # Reconfigure PLL to change sys_clk clkout0_clkreg1.high_time = vco_div // 2 + vco_div % 2 clkout0_clkreg1.low_time = vco_div // 2 uspll.write(0x08, clkout0_clkreg1.pack()) # Measure/verify sys_clk duration = 5e-1 start = bus.regs.crg_sys_clk_counter.read() time.sleep(duration) end = bus.regs.crg_sys_clk_counter.read() print("Measured sys_clk: {:3.2f}MHz.".format( (end - start) / (1e6 * duration))) # Reboot SoC and log BIOS output print("-" * 40) print("Reboot SoC and get BIOS log...") print("-" * 40) ctrl.reboot() start = time.time() while (time.time() - start) < bios_timeout: if bus.regs.uart_xover_rxfull.read(): length = 16 elif not bus.regs.uart_xover_rxempty.read(): length = 1 else: time.sleep(1e-3) continue for c in bus.read(bus.regs.uart_xover_rxtx.addr, length=length, burst="fixed"): print("{:c}".format(c), end="") print("") # # # bus.close()
from litex import RemoteClient wb = RemoteClient() wb.open() # # # identifier = "" for i in range(30): identifier += chr(wb.read(wb.bases.identifier_mem + 4 * (i + 1))) # TODO: why + 1? print(identifier) print("frequency : {}MHz".format(wb.constants.system_clock_frequency / 1000000)) print("link up : {}".format(wb.regs.pcie_phy_lnk_up.read())) print("bus_master_enable : {}".format( wb.regs.pcie_phy_bus_master_enable.read())) print("msi_enable : {}".format(wb.regs.pcie_phy_msi_enable.read())) print("max_req_request_size : {}".format( wb.regs.pcie_phy_max_request_size.read())) print("max_payload_size : {}".format(wb.regs.pcie_phy_max_payload_size.read())) # # # wb.close()
from litex import RemoteClient from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver wb = RemoteClient(port=1234) wb.open() identifier = "" for i in range(0, 32): identifier += "%c" %wb.read(wb.bases.identifier_mem + 4*i) print("\nSoC identifier: " + identifier) print() # # # analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True) analyzer.configure_trigger(cond={ # "soc_sender_source_source_valid": 1, # "soc_sender_source_source_ready": 1, # "soc_sender_source_source_payload_data": 0 "soc_ulpi_core0_source_source_valid": 1, "soc_ulpi_core0_source_source_ready": 1, }) # analyzer.configure_trigger() analyzer.configure_subsampler(1) analyzer.run(offset=1, length=1024) analyzer.wait_done() analyzer.upload() analyzer.save("dump.vcd") # # #
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 0 * 4, 16)])) #print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 4 * 4 * 4, 16)])) #print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 8 * 4 * 4, 16)])) #print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 12 * 4 * 4, 16)])) # FIXME: random #off = 67108864 - 100 #wb.write(0x40000000 + off * 4, 0xffffefff) # -------------------------------------------------------------------- import random from datetime import datetime offset = random.Random(datetime.now()).randrange( 0x0, 256 * 1024 * 1024 - 32) # FIXME: Check corner case print('offset: ' + str(offset) + ', expecting: ' + str((offset // 16) * 16)) wb.write(0x40000000 + offset, wb.read(0x40000000 + offset) ^ 0x000010000) # -------------------------------------------------------------------- #print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 0 * 4, 16)])) #print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 4 * 4 * 4, 16)])) #print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 8 * 4 * 4, 16)])) #print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 12 * 4 * 4, 16)])) wb.regs.reader_start.write(0) wb.regs.reader_reset.write(1) time.sleep(10000 / 1e6) wb.regs.reader_reset.write(0) # Expected pattern wb.write(0x30000000, 0xffffffff) # patttern wb.write(0x31000000, 0xffffffff) # patttern