def __init__(self,
pnr_placer="heap",
pnr_seed=0,
debug=True,
boot_vector=0x20020000,
**kwargs):
"""Create a basic SoC for iCEBreaker.
Create a basic SoC for iCEBreaker. The `sys` frequency will run at 12 MHz.
Args:
pnr_placer (str): Which placer to use in nextpnr
pnr_seed (int): Which seed to use in nextpnr
Returns:
Newly-constructed SoC
"""
platform = Platform()
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = None
kwargs["cpu_variant"] = None
else:
kwargs["cpu_reset_address"] = boot_vector
clk_freq = int(12e6)
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
if debug:
kwargs["uart_name"] = "crossover"
if kwargs["cpu_type"] == "vexriscv":
kwargs["cpu_variant"] = kwargs["cpu_variant"] + "+debug"
SoCCore.__init__(self,
platform,
clk_freq,
with_uart=True,
with_ctrl=True,
**kwargs)
# If there is a VexRiscv CPU, add a fake ROM that simply tells the CPU
# to jump to the given address.
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.add_memory_region("rom", 0, 16)
self.submodules.rom = JumpToAddressROM(16, boot_vector)
self.submodules.crg = _CRG(platform)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlash(spi_pads,
dummy=6,
endianness="little")
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=16 * 1024 * 1024)
self.add_csr("lxspi")
# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
# however you can use the "crossover" UART to communicate with this over the bridge.
if debug:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
ledsignals = Signal(2)
self.submodules.leds = GPIOOut(ledsignals)
self.comb += platform.request("user_ledr_n").eq(ledsignals[0])
self.comb += platform.request("user_ledg_n").eq(ledsignals[1])
self.add_csr("leds")
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.yosys_template[
2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
# if use_dsp:
# platform.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[
2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if pnr_placer is not None:
platform.toolchain.build_template[1] += " --placer {}".format(
pnr_placer)
def __init__(self, flash_offset, sys_clk_freq, **kwargs):
"""Create a basic SoC for iCEBreaker.
Returns:
Newly-constructed SoC
"""
platform = Platform()
# Use SERV CPU buy default
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = "serv"
kwargs["cpu_variant"] = "standard"
else:
if kwargs["cpu_type"] == "vexriscv" and ("cpu_variant"
not in kwargs):
kwargs["cpu_variant"] = "minimal"
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset
# SoCCore
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spiflash_size = 16 * 1024 * 1024
self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"),
dummy=6,
endianness="little")
self.add_csr("spiflash")
# SPI flash cache
l2_cache_size = 8192
if l2_cache_size != 0:
self.submodules.l2_cache = wishbone.Cache(
cachesize=l2_cache_size // 4,
master=wishbone.Interface(32),
slave=self.spiflash.bus,
)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.l2_cache.master,
size=spiflash_size)
else:
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=spiflash_size)
# Add ROM linker region
self.add_memory_region("rom",
self.mem_map["spiflash"] + flash_offset,
spiflash_size - flash_offset,
type="cached+linker")
# User button as reset
reset_btn = platform.request("user_btn_n")
self.comb += self.crg.reset.eq(~reset_btn)
# Clock peripheral holds the actual sys_clk frequency
self.submodules.clock = ClockPeripheral(sys_clk_freq)
self.add_csr("clock")
# GPIO peripheral
pin_names = ["PMOD1A:%d" % i for i in range(8)] +\
["PMOD1B:%d" % i for i in range(8)] +\
["PMOD2:%d" % i for i in range(8)]
gpio_extension = [("gpio", i, Pins(name), IOStandard("LVCMOS33"))
for i, name in enumerate(pin_names)]
platform.add_extension(gpio_extension)
gpio = []
for i in range(len(pin_names)):
gpio.append(platform.request("gpio"))
self.submodules.gpio = GPIOPeripheral(gpio + [
platform.request("user_ledr_n"),
platform.request("user_ledg_n"),
])
self.add_csr("gpio")
# Suppress synthesis output
assert hasattr(self.platform.toolchain, "build_template")
if self.platform.toolchain.build_template[0].startswith("yosys "):
self.platform.toolchain.build_template[0] = \
self.platform.toolchain.build_template[0].replace("yosys ", "yosys -q ")
def __init__(self, debug, flash_offset, sys_clk_freq, **kwargs):
"""Create a basic SoC for iCEBreaker.
Create a basic SoC for iCEBreaker. The `sys` frequency will run at 12 MHz.
Returns:
Newly-constructed SoC
"""
platform = Platform()
# Set cpu name and variant defaults when none are provided
if "cpu_variant" not in kwargs:
if debug:
kwargs["cpu_variant"] = "lite+debug"
else:
kwargs["cpu_variant"] = "lite"
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
kwargs["csr_data_width"] = 32
# Set CPU reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset
# Select "crossover" as soc uart instead of "serial"
# We have to make that selection before calling the parent initializer
if debug:
kwargs["uart_name"] = "crossover"
# SoCCore
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spiflash_size = 16 * 1024 * 1024
self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"),
dummy=6,
endianness="little")
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=spiflash_size)
self.add_csr("spiflash")
# Add ROM linker region
self.add_memory_region("rom",
self.mem_map["spiflash"] + flash_offset,
spiflash_size - flash_offset,
type="cached+linker")
# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
# however you can use the "crossover" UART to communicate with this over the bridge.
if debug:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
platform.add_extension(break_off_pmod)
self.submodules.leds = Leds(
Cat(platform.request("user_ledr_n"),
platform.request("user_ledg_n"), platform.request("user_ledr"),
platform.request("user_ledg", 0),
platform.request("user_ledg", 1),
platform.request("user_ledg", 2),
platform.request("user_ledg", 3)),
led_polarity=0x03,
led_name=[["ledr", "The Red LED on the main iCEBreaker board."],
["ledg", "The Green LED on the main iCEBreaker board."],
[
"hledr1",
"The center Red LED #1 on the iCEBreaker head."
], ["hledg2", "Green LED #2 on the iCEBreaker head."],
["hledg3", "Green LED #3 on the iCEBreaker head."],
["hledg4", "Green LED #4 on the iCEBreaker head."],
["hledg5", "Green LED #5 on the iCEBreaker head."]])
self.add_csr("leds")
def __init__(self, sys_clk_freq, **kwargs):
platform = Platform()
kwargs["cpu_type"] = None
kwargs["with_uart"] = False
kwargs["with_timer"] = False
#kwargs["with_ctrl"] = False
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
kwargs["csr_data_width"] = 32
clock_ext = [
("clk16", 0, Pins("20"), IOStandard("LVCMOS33"))
]
platform.add_extension(clock_ext)
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
reset_btn = platform.request("user_btn_n")
self.comb += self.crg.reset.eq(~reset_btn)
led = platform.request("user_led_n")
led2 = platform.request("user_led_n")
spi_ext = [
("spi_slave", 0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("17"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("14"), IOStandard("LVCMOS33")),
),
]
platform.add_extension(spi_ext)
spi_pads = platform.request("spi_slave")
self.submodules.bridge = bridge = SPIBridge(spi_pads)
self.bus.add_master(name="bridge", master=self.bridge.wishbone)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
# spram_size = 128 * 1024
# self.submodules.spram = Up5kSPRAM(size=spram_size)
# self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
# spiflash_size = 16 * 1024 * 1024
# self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little")
# self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=spiflash_size)
# self.add_csr("spiflash")
# Add ROM linker region
#self.add_memory_region("rom", self.mem_map["spiflash"] + flash_offset, spiflash_size - flash_offset, type="cached+linker")
platform.add_extension(break_off_pmod)
self.submodules.leds = Leds(Cat(
#platform.request("user_ledr_n"),
#platform.request("user_ledg_n"),
platform.request("user_ledr"),
platform.request("user_ledg", 0),
platform.request("user_ledg", 1),
platform.request("user_ledg", 2),
platform.request("user_ledg", 3)),
led_polarity=0x00,
led_name=[
#["ledr", "The Red LED on the main iCEBreaker board."],
#["ledg", "The Green LED on the main iCEBreaker board."],
["hledr1", "The center Red LED #1 on the iCEBreaker head."],
["hledg2", "Green LED #2 on the iCEBreaker head."],
["hledg3", "Green LED #3 on the iCEBreaker head."],
["hledg4", "Green LED #4 on the iCEBreaker head."],
["hledg5", "Green LED #5 on the iCEBreaker head."]])
self.add_csr("leds")
assert hasattr(self.platform.toolchain, "build_template")
if self.platform.toolchain.build_template[0].startswith("yosys "):
self.platform.toolchain.build_template[0] =\
self.platform.toolchain.build_template[0].replace("yosys ", "yosys -q ")
def __init__(self, debug=True, boot_vector=0x20040000, **kwargs):
"""Create a basic SoC for iCEBreaker.
Create a basic SoC for iCEBreaker. The `sys` frequency will run at 12 MHz.
Returns:
Newly-constructed SoC
"""
platform = Platform()
kwargs["cpu_variant"] = "lite"
kwargs["cpu_reset_address"] = boot_vector
if debug:
kwargs["uart_name"] = "crossover"
kwargs["cpu_variant"] = "lite+debug"
clk_freq = int(12e6)
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
SoCCore.__init__(self, platform, clk_freq, **kwargs)
# If there is a VexRiscv CPU, add a fake ROM that simply tells the CPU
# to jump to the given address.
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.add_memory_region("rom", 0, 16)
self.submodules.rom = JumpToAddressROM(16, boot_vector)
self.submodules.crg = _CRG(platform)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlash(spi_pads,
dummy=6,
endianness="little")
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=16 * 1024 * 1024)
self.add_csr("lxspi")
# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
# however you can use the "crossover" UART to communicate with this over the bridge.
if debug:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
self.submodules.leds = Leds(
Cat(platform.request("user_ledr_n"),
platform.request("user_ledg_n")),
led_polarity=0x03,
led_name=[["ledr", "The Red LED on the main iCEBreaker board."],
["ledg", "The Green LED on the main iCEBreaker board."]])
self.add_csr("leds")