def test_610_TRXC_A32(self): log.warn("=== A32 TRX command: TX1/TX2 transfer test ===") brd = self.brd1 cpu = brd.cpu # A404_ENH_MODE only if brd.skipIfNotBrd('A404_ENH_MODE', 'test'): return brd.enableA32() brd.initBoard(0) log.info("transfer commands (TXCOM1-->RXCOM2)") for cmmd in self.cmmdTbl: brd.sendCmd(1, cmmd) brd.recvVeriCmd(2, cmmd) log.info("transfer commands (TXCOM2-->RXCOM1)") for cmmd in self.cmmdTbl: brd.sendCmd(2, cmmd) brd.recvVeriCmd(1, cmmd) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) brd.disableA32()
def test_315_SDRAM_A32BLK(self): log.warn("=== A32BLK access to SDRAM (A404 enhanced mode) ===") brd = self.brd1 cpu = brd.cpu # A404_ENH_MODE only if brd.skipIfNotBrd('A404_ENH_MODE', 'test'): return brd.enableA32() for spacename, offs in self.sdramRxTbl(brd).items(): startaddr = brd.vmeAddr + offs endaddr = startaddr + brd.TRX_SIZE - 1 log.info("access %s" % spacename) # D32 cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a32d32,10\"" % \ (startaddr, endaddr, mtestMaxErr) execCmdSucc(cpu.cons, cmmd, 0) # D64 cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a32d64,10\"" % \ (startaddr, endaddr, mtestMaxErr) execCmdSucc(cpu.cons, cmmd, 0) brd.disableA32()
def _TRXD_A24(self, loop): brd = self.brd1 cpu = brd.cpu brd.initBoard(loop) for t in brd.accTbl: log.warn("---------- %s ----------" % tInfo(t)) if loop: self.trxData1_2('tx1', 'rx1', t) self.trxData1_2('tx2', 'rx2', t) else: self.trxData1_2('tx1', 'rx2', t) self.trxData1_2('tx2', 'rx1', t) self.trxData12(t) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) # A404 only if 0 == brd.skipIfBrd('OLD_CME', 'blk test'): for mod in ['a24d16', 'a24d32']: log.warn("---------- blk %s ----------" % mod) self.trxBlkData12(mod) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) if loop: brd.disableHwLoop()
def test_700_IRQ_BASIC(self): log.warn("=== BASIC IRQ test ===") brd = self.brd1 brd.initBoard(0) self.irqBasicTest(1, 2, 5, 102) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
def test_525_TRXD_A24_LOOP(self): log.warn("=== HW-LOOP - A24 TRX data: TX1/TX2/TX12 transfer test ===") brd = self.brd1 # A404 only if brd.skipIfBrd('OLD_CME', 'test'): return self._TRXD_A24(1)
def test_510_TRXD_BASIC_LOOP(self): log.warn("=== HW-LOOP - A24 TRX data: basic transfer test ===") brd = self.brd1 # A404 only if brd.skipIfBrd('OLD_CME', 'test'): return self._TRXD_BASIC(1)
def test_605_TRXC_A24_LOOP(self): log.warn("=== HW-LOOP - A24 TRX command: TX1/TX2 transfer test ===") brd = self.brd1 # A404 only if brd.skipIfBrd('OLD_CME', 'test'): return self._TRXC_A24(1)
def test_710_IRQ_A24(self): log.warn("=== A24 IRQ stress test ===") brd = self.brd1 cpu = brd.cpu brd.initBoard(0) log.info("IRQ test:") cmmd = "a404IrqTest( 0x%x, %d )" % (brd.base, brd.enh) execCmdSucc(cpu.cons, cmmd, 0) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
def test_200_VMEREGS_A24(self): log.warn("=== A24 access to VME-Registers ===") brd = self.brd1 cpu = brd.cpu for regname, offs in self.vmeRegTbl.items(): startaddr = brd.base + brd.RXC + offs cmmd = "mtest \"0x%x 0x%x -n=3 -o=2 -q=%d -t=%s\"" % \ (startaddr, startaddr+1, mtestMaxErr, brd.accOpt) log.info("access %s" % regname) execCmdSucc(cpu.cons, cmmd, 0)
def test_705_IRQ_BASIC_LOOP(self): log.warn("=== HW-LOOP - BASIC IRQ test ===") brd = self.brd1 # A404 only if brd.skipIfBrd('OLD_CME', 'test'): return brd.initBoard(1) self.irqBasicTest(1, 1, 5, 102) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) brd.disableHwLoop()
def test_300_SDRAM_A24(self): log.warn("=== A24 access to SDRAM ===") brd = self.brd1 cpu = brd.cpu for spacename, offs in self.sdramRxTbl(brd).items(): startaddr = brd.base + offs endaddr = startaddr + brd.TRX_SIZE - 1 cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=%s\"" % \ (startaddr, endaddr, mtestMaxErr, brd.accOpt) log.info("access %s" % spacename) execCmdSucc(cpu.cons, cmmd, 0)
def test_800_DISCON(self): log.warn("=== Disconnection test: get TX/RX status ===") brd = self.brd1 cpu = brd.cpu brd.initBoard(0) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) userReady("Please remove the TX1->RX2, TX2->RX1 wires") for ch in [1, 2]: ret = brd.getClrRxstat(ch) log.info("check RXSTAT%d for !CONNECTED" % ch) if ret & RXSTAT_CONNECT == RXSTAT_CONNECT: log.error(cmmd + ' : failed') self.fail("RXSTAT::CONNECTED bit set") # not OLD_CME if brd.skipIfBrd('OLD_CME', 'TX status check') == 0: brd.clrTxstat(1) brd.clrTxstat(2) # write words to tx1/2 brd.tx('tx12', 'w') brd.checkClrTxstat(1, 0x01) brd.checkClrTxstat(2, 0x01) brd.checkClrTxstat(1, 0x00) brd.checkClrTxstat(2, 0x00) for loop in [0, 1]: for n in range(0, 5): brd.initBoard(loop) for ch in [1, 2]: ret = brd.getClrRxstat(ch) if ret & RXSTAT_CRCERR == RXSTAT_CRCERR: self.fail("RXSTAT::RCV_CRC_ERR bit set") if ret & RXSTAT_DATALOST == RXSTAT_DATALOST: self.fail("RXSTAT::RXSTAT_DATALOST bit set") userReady("Please re-plug the TX1->RX2, TX2->RX1 wires") for ch in [1, 2]: ret = brd.getClrRxstat(ch) log.info("check RXSTAT%d for CONNECTED" % ch) if ret & RXSTAT_CONNECT != RXSTAT_CONNECT: log.error(cmmd + ' : failed') self.fail("RXSTAT::CONNECTED bit not set")
def test_320_SDRAM_TX12_DUPLICATION(self): log.warn("=== TX12 duplication to TX1/TX2 ===") brd = self.brd1 cpu = brd.cpu # not A404_ENH_MODE if brd.skipIfBrd('A404_ENH_MODE', 'test'): return brd.clrRx('tx1') brd.clrRx('tx2') brd.tx('tx12', 'w') brd.rx('tx1', 'w') brd.rx('tx2', 'w')
def test_820_RXFIFO(self): log.warn("=== Receiver Fifo test: get RX status ===") brd = self.brd1 cpu = brd.cpu # A404 only if brd.skipIfBrd('OLD_CME', 'test'): return brd.initBoard(0) for rxCh in (1, 2): log.info("RX%d: Receiver Fifo test" % rxCh) cmmd = "a404RxFifoTest( 0x%x, %d, %d )" % \ (brd.base, brd.enh, rxCh) execCmdSucc(cpu.cons, cmmd, 0)
def test_720_IRQ_A32(self): log.warn("=== A32 IRQ stress test ===") brd = self.brd1 cpu = brd.cpu # A404_ENH_MODE only if brd.skipIfNotBrd('A404_ENH_MODE', 'test'): return brd.enableA32() brd.initBoard(0) log.info("IRQ test:") cmmd = "a404IrqTest( 0x%x, %d )" % (brd.base, brd.enh) execCmdSucc(cpu.cons, cmmd, 0) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) brd.disableA32()
def test_210_VMEREGS_A32(self): log.warn("=== A32 access to VME-Registers ===") brd = self.brd1 cpu = brd.cpu # A404_ENH_MODE only if brd.skipIfNotBrd('A404_ENH_MODE', 'test'): return brd.enableA32() for regname, offs in self.vmeRegTbl.items(): startaddr = brd.base + brd.RXC + offs cmmd = "mtest \"0x%x 0x%x -n=3 -o=2 -q=%d -t=%s\"" % \ (startaddr, startaddr+1, mtestMaxErr, brd.accOpt) log.info("access %s" % regname) execCmdSucc(cpu.cons, cmmd, 0) brd.disableA32()
def test_310_SDRAM_A32(self): log.warn("=== A32 access to SDRAM (A404 enhanced mode) ===") brd = self.brd1 cpu = brd.cpu # A404_ENH_MODE only if brd.skipIfNotBrd('A404_ENH_MODE', 'test'): return brd.enableA32() for spacename, offs in self.sdramRxTbl(brd).items(): startaddr = brd.base + offs endaddr = startaddr + brd.TRX_SIZE - 1 cmmd = "mtest \"0x%x 0x%x -n=3 -o=2 -q=%d -t=%s\"" % \ (startaddr, endaddr, mtestMaxErr, brd.accOpt) log.info("access %s" % spacename) execCmdSucc(cpu.cons, cmmd, 0) brd.disableA32()
def test_305_SDRAM_A24BLK(self): log.warn("=== A24BLK access to SDRAM ===") brd = self.brd1 cpu = brd.cpu # A404 only if brd.skipIfBrd('OLD_CME', 'test'): return for spacename, offs in self.sdramRxTbl(brd).items(): startaddr = brd.vmeAddr + offs endaddr = startaddr + brd.TRX_SIZE - 1 log.info("access %s" % spacename) # D16 cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a24d16,10\"" % \ (startaddr, endaddr, mtestMaxErr) execCmdSucc(cpu.cons, cmmd, 0) # D32 cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a24d32,10\"" % \ (startaddr, endaddr, mtestMaxErr) execCmdSucc(cpu.cons, cmmd, 0)
def test_400_LEDS(self): log.warn("=== toggle LEDs ===") brd = self.brd1 cpu = brd.cpu # A404 only if brd.skipIfBrd('OLD_CME', 'test'): return brd.disableTX1TX2() brd.getClrRxstat(1) brd.getClrRxstat(2) cmmd = "a404ToggleLeds(0x%x, %d)" % (brd.base, brd.enh) userReady("Please verify the coming LED states:\n" \ " 1. ch#1: LEDs goes/remain ON in the order: rx-red, rx-yellow, rx-green, tx-yellow, tx-green\n" \ " 2. ch#1: all LEDs restored to origin states\n" \ " 3. step 1..2 repeated for ch#2") execCmdSucc(cpu.cons, cmmd, 0) brd.enableTX1TX2() userVerified(self)
def _TRXD_A32(self, loop): brd = self.brd1 cpu = brd.cpu # A404_ENH_MODE only if brd.skipIfNotBrd('A404_ENH_MODE', 'test'): return brd.enableA32() brd.initBoard(loop) for t in brd.accTbl: log.warn("---------- %s ----------" % tInfo(t)) self.trxData12(t) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) for mod in ['a32d32', 'a32d64']: log.warn("---------- blk %s ----------" % mod) self.trxBlkData12(mod) brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO) if loop: brd.disableHwLoop() brd.disableA32()
def test_810_CRCERR(self): log.warn("=== CRC error detection test: get RX status ===") brd = self.brd1 cpu = brd.cpu brd.initBoard(0) log.info("TX1/TX2: enable CRC error insertion") for ch in [1, 2]: cmmd = "a404ByteRegSetmask( 0x%x, %d, %d, 0x%x, 0x%x )" % \ (brd.base, brd.enh, ch, TXCTRL, TXCTRL_CRCERR) execCmdSucc(cpu.cons, cmmd, 0) # write 2 words to tx1/2 brd.txn('tx12', 2, 'w') for ch in [1, 2]: log.info("check RXSTAT%d for RCV_CRC_ERR (and clear)" % ch) # OLD_CME if brd.type == 'OLD_CME': log.info("OLD_CME: FIFO will be emptied by repeating the " "clear" "") ret = brd.getClrRxstat(ch) if ret & RXSTAT_CRCERR != RXSTAT_CRCERR: self.fail("RXSTAT::RCV_CRC_ERR bit not set") ret = brd.getClrRxstat(ch) if ret & RXSTAT_CRCERR == RXSTAT_CRCERR: self.fail("RXSTAT::RCV_CRC_ERR bit set") if ret & RXSTAT_DATALOST != RXSTAT_DATALOST: self.fail("RXSTAT::RXSTAT_DATALOST bit not set") ret = brd.getClrRxstat(ch) ret = brd.getClrRxstat(ch) if ret & RXSTAT_CRCERR == RXSTAT_CRCERR: self.fail("RXSTAT::RCV_CRC_ERR bit set") if ret & RXSTAT_DATALOST == RXSTAT_DATALOST: self.fail("RXSTAT::RXSTAT_DATALOST bit set") # A404 else: log.info("A404: Different behaviour as OLD_CME") ret = brd.getClrRxstat(ch) if ret & RXSTAT_CRCERR != RXSTAT_CRCERR: self.fail("RXSTAT::RCV_CRC_ERR bit not set") if ret & RXSTAT_DATALOST != RXSTAT_DATALOST: self.fail("RXSTAT::RXSTAT_DATALOST bit not set") ret = brd.getClrRxstat(ch) if ret & RXSTAT_CRCERR == RXSTAT_CRCERR: self.fail("RXSTAT::RCV_CRC_ERR bit set") if ret & RXSTAT_DATALOST == RXSTAT_DATALOST: self.fail("RXSTAT::RXSTAT_DATALOST bit set") log.info("TX1/TX2: disable CRC error insertion") for ch in [1, 2]: cmmd = "a404ByteRegClrmask( 0x%x, %d, %d, 0x%x, 0x%x )" % \ (brd.base, brd.enh, ch, TXCTRL, TXCTRL_CRCERR) execCmdSucc(cpu.cons, cmmd, 0) # write 2 words to tx1/2 brd.txn('tx12', 2, 'w') brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
def test_500_TRXD_BASIC(self): log.warn("=== A24 TRX data: basic transfer test ===") self._TRXD_BASIC(0)
def test_520_TRXD_A24(self): log.warn("=== A24 TRX data: TX1/TX2/TX12 transfer test ===") self._TRXD_A24(0)
def test_900_BENCH(self): log.warn("=== simple benchmark test ===") self._BENCH(0, 0) self._BENCH(0, 1)
def test_600_TRXC_A24(self): log.warn("=== A24 TRX command: TX1/TX2 transfer test ===") self._TRXC_A24(0)
def test_535_TRXD_A32_LOOP(self): log.warn("=== HW-LOOP - A32 TRX data: TX12 transfer test ===") self._TRXD_A32(1)
def test_910_BENCH_LOOP(self): log.warn("=== HW-LOOP - simple benchmark test ===") self._BENCH(1, 0) self._BENCH(1, 1)
def test_530_TRXD_A32(self): log.warn("=== A32 TRX data: TX12 transfer test ===") self._TRXD_A32(0)