def get_drain_cin(self): """Get the relative capacitance of the drain of the PMOS isolation TX""" from tech import parameter #Bitcell drain load being used to estimate PMOS drain load drain_load = logical_effort.convert_farad_to_relative_c( parameter['bitcell_drain_cap']) return drain_load
def analytical_delay(self, slews, loads): """ Return the analytical model results for the SRAM. """ if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0: debug.warning("Analytical characterization results are not supported for multiport.") self.create_signal_names() self.create_measurement_names() power = self.analytical_power(slews, loads) port_data = self.get_empty_measure_data_dict() relative_loads = [logical_effort.convert_farad_to_relative_c(c_farad) for c_farad in loads] for slew in slews: for load in relative_loads: self.set_load_slew(load,slew) bank_delay = self.sram.analytical_delay(self.corner, self.slew,self.load) for port in self.all_ports: for mname in self.delay_meas_names+self.power_meas_names: if "power" in mname: port_data[port][mname].append(power.dynamic) elif "delay" in mname: port_data[port][mname].append(bank_delay[port].delay/1e3) elif "slew" in mname: port_data[port][mname].append(bank_delay[port].slew/1e3) else: debug.error("Measurement name not recognized: {}".format(mname),1) period_margin = 0.1 risefall_delay = bank_delay[self.read_ports[0]].delay/1e3 sram_data = { "min_period":risefall_delay*2*period_margin, "leakage_power": power.leakage} debug.info(2,"SRAM Data:\n{}".format(sram_data)) debug.info(2,"Port Data:\n{}".format(port_data)) return (sram_data,port_data)
def analytical_delay(self, corner, slew, load): from tech import parameter """Returns relative delay that the column mux adds""" #Single level column mux will add parasitic loads from other mux pass transistors and the sense amp. drain_load = logical_effort.convert_farad_to_relative_c( parameter['bitcell_drain_cap']) array_load = drain_load * self.words_per_row return [self.mux.analytical_delay(corner, slew, load + array_load)]
def analytical_delay(self, corner, slew, load): """Returns relative delay of the bitline in the bitcell array""" from tech import parameter #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux. #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics. drain_load = logical_effort.convert_farad_to_relative_c( parameter['bitcell_drain_cap']) wire_unit_load = .05 * drain_load #Wires add 5% to this. bitline_load = (drain_load + wire_unit_load) * self.row_size return [self.cell.analytical_delay(corner, slew, load + bitline_load)]
def analytical_delay(self, corner, slew, load=0, swing=0.5): parasitic_delay = 1 size = 0.5 #This accounts for bitline being drained thought the access TX and internal node cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file. #Internal loads due to port configs are halved. This is to account for the size already being halved #for stacked TXs, but internal loads do not see this size estimation. write_port_load = self.num_w_ports * logical_effort.convert_farad_to_relative_c( parameter['bitcell_drain_cap']) / 2 read_port_load = self.num_r_ports / 2 #min size NMOS gate load total_load = load + read_port_load + write_port_load return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
def analytical_delay(self, corner, slew, load=0.0): """Inform users undefined delay module while building new modules""" # FIXME: Slew is not used in the model right now. Can be added heuristically as linear factor relative_cap = logical_effort.convert_farad_to_relative_c(load) stage_effort = self.get_stage_effort(relative_cap) # If it fails, then keep running with a valid object. if stage_effort == None: return delay_data(0.0, 0.0) abs_delay = stage_effort.get_absolute_delay() corner_delay = self.apply_corners_analytically(abs_delay, corner) SLEW_APPROXIMATION = 0.1 corner_slew = SLEW_APPROXIMATION * corner_delay return delay_data(corner_delay, corner_slew)