class Riscv(Platform): type = 'Riscv' cxx_header = "dev/riscv/Riscv.hh" system = Param.System(Parent.any, "system") print("Enter Riscv(Platform)") com_1 = Uart8250(pio_addr = 0x80013070) com_1.device = Terminal() def attachIO(self, bus): self.com_1.pio = bus.master
class Pc(Platform): type = 'Pc' cxx_header = "dev/x86/pc.hh" cxx_class = 'gem5::Pc' system = Param.System(Parent.any, "system") south_bridge = Param.SouthBridge(SouthBridge(), "Southbridge") pci_host = PcPciHost() # Serial port and terminal com_1 = Uart8250() com_1.pio_addr = x86IOAddress(0x3f8) com_1.device = Terminal() # Devices to catch access to non-existant serial ports. fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8) fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8) fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8) # A device to catch accesses to the non-existant floppy controller. fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2) # A bus for accesses not claimed by a specific device. default_bus = IOXBar() # A device to handle accesses to unclaimed IO ports. empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64KiB', ret_data8=0, ret_data16=0, ret_data32=0, ret_data64=0, pio=default_bus.mem_side_ports) # A device to handle any other type of unclaimed access. bad_addr = BadAddr(pio=default_bus.default) def attachIO(self, bus, dma_ports=[]): self.south_bridge.attachIO(bus, dma_ports) self.com_1.pio = bus.mem_side_ports self.fake_com_2.pio = bus.mem_side_ports self.fake_com_3.pio = bus.mem_side_ports self.fake_com_4.pio = bus.mem_side_ports self.fake_floppy.pio = bus.mem_side_ports self.pci_host.pio = bus.mem_side_ports self.default_bus.cpu_side_ports = bus.default
class Pc(Platform): type = 'Pc' cxx_header = "dev/x86/pc.hh" system = Param.System(Parent.any, "system") south_bridge = SouthBridge() pci_host = PcPciHost() # "Non-existant" ports used for timing purposes by the linux kernel i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1) # Ports behind the pci config and data regsiters. These don't do anything, # but the linux kernel fiddles with them anway. behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) # Serial port and terminal com_1 = Uart8250() com_1.pio_addr = x86IOAddress(0x3f8) com_1.device = Terminal() # Devices to catch access to non-existant serial ports. fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8) fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8) fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8) # A device to catch accesses to the non-existant floppy controller. fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2) # NVMe Interface nvme = NVMeInterface(pci_func=0, pci_dev=5, pci_bus=0) def attachIO(self, bus, dma_ports=[]): self.south_bridge.attachIO(bus, dma_ports) self.i_dont_exist1.pio = bus.master self.i_dont_exist2.pio = bus.master self.behind_pci.pio = bus.master self.com_1.pio = bus.master self.fake_com_2.pio = bus.master self.fake_com_3.pio = bus.master self.fake_com_4.pio = bus.master self.fake_floppy.pio = bus.master self.pci_host.pio = bus.default self.nvme.pio = bus.master if dma_ports.count(self.nvme.dma) == 0: self.nvme.dma = bus.slave
class VExpress_GEM5_Base(RealView): """ The VExpress gem5 memory map is loosely based on a modified Versatile Express RS1 memory map. The gem5 platform has been designed to implement a subset of the original Versatile Express RS1 memory map. Off-chip peripherals should, when possible, adhere to the Versatile Express memory map. Non-PCI off-chip devices that are gem5-specific should live in the CS5 memory space to avoid conflicts with existing devices that we might want to model in the future. Such devices should normally have interrupts in the gem5-specific SPI range. On-chip peripherals are loosely modeled after the ARM CoreTile Express A15x2 memory and interrupt map. In particular, the GIC and Generic Timer have the same interrupt lines and base addresses. Other on-chip devices are gem5 specific. Unlike the original Versatile Express RS2 extended platform, gem5 implements a large contigious DRAM space, without aliases or holes, starting at the 2GiB boundary. This means that PCI memory is limited to 1GiB. References: Technical Reference Manuals: Arm Motherboard Express uATX (V2M-P1) - ARM DUI 0447J Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E Official Linux device tree specifications: V2M-P1 - arch/arm/boot/dts/vexpress-v2m-rs1.dtsi V2P-CA15 - arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts Memory map: Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E Daughterboard (global) Section 3.2.1 - Table 3-1 - Daughterboard memory map On-chip Section 3.2.3 - Table 3-2 - Cortex-A15 MPCore on-chip peripheral memory map Interrupts: Arm CoreTile Express A15x2 (V2P-CA15) - ARM DUI 0604E Section 2.8.2 - Test chip interrupts Memory map: 0x00000000-0x03ffffff: Boot memory (CS0) 0x04000000-0x07ffffff: Reserved 0x08000000-0x0bffffff: NOR FLASH0 (CS0 alias) 0x0c000000-0x0fffffff: NOR FLASH1 (Off-chip, CS4) 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 0x10000000-0x1000ffff: gem5 energy controller 0x10010000-0x1001ffff: gem5 pseudo-ops 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 0x1c060000-0x1c06ffff: KMI0 (keyboard) 0x1c070000-0x1c07ffff: KMI1 (mouse) 0x1c090000-0x1c09ffff: UART0 0x1c0a0000-0x1c0affff: UART1 0x1c0b0000-0x1c0bffff: UART2 0x1c0c0000-0x1c0cffff: UART3 0x1c0f0000-0x1c0fffff: Watchdog (SP805) 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension) 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension) 0x1c170000-0x1c17ffff: RTC 0x20000000-0x3fffffff: On-chip peripherals: 0x2a430000-0x2a43ffff: System Counter (control) 0x2a490000-0x2a49ffff: Trusted Watchdog (SP805) 0x2a800000-0x2a800fff: System Counter (read) 0x2a810000-0x2a810fff: System Timer (control) 0x2a820000-0x2a820fff: System Timer (frame 0) 0x2a830000-0x2a830fff: System Timer (frame 1) 0x2b000000-0x2b00ffff: HDLCD 0x2b060000-0x2b060fff: System Watchdog (SP805) 0x2b400000-0x2b41ffff: SMMUv3 0x2c001000-0x2c001fff: GIC (distributor) 0x2c002000-0x2c003fff: GIC (CPU interface) 0x2c004000-0x2c005fff: vGIC (HV) 0x2c006000-0x2c007fff: vGIC (VCPU) 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 0x2d000000-0x2d00ffff: GPU (reserved) 0x2f000000-0x2fffffff: PCI IO space 0x30000000-0x3fffffff: PCI config space 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 0x80000000-X: DRAM Interrupts: 0- 15: Software generated interrupts (SGIs) 16- 31: On-chip private peripherals (PPIs) 25 : vgic 26 : generic_timer (hyp) 27 : generic_timer (virt) 28 : Reserved (Legacy FIQ) 29 : generic_timer (phys, sec) 30 : generic_timer (phys, non-sec) 31 : Reserved (Legacy IRQ) 32- 95: Mother board peripherals (SPIs) 32 : Watchdog (SP805) 33 : Reserved (IOFPGA SW int) 34-35: Reserved (SP804) 36 : RTC 37-40: uart0-uart3 41-42: Reserved (PL180) 43 : Reserved (AACI) 44-45: kmi0-kmi1 46 : Reserved (CLCD) 47 : Reserved (Ethernet) 48 : Reserved (USB) 56 : Trusted Watchdog (SP805) 57 : System timer0 (phys) 58 : System timer1 (phys) 95-255: On-chip interrupt sources (we use these for gem5-specific devices, SPIs) 74 : VirtIO (gem5/FM extension) 75 : VirtIO (gem5/FM extension) 95 : HDLCD 96- 98: GPU (reserved) 100-103: PCI 130 : System Watchdog (SP805) 256-319: MSI frame 0 (gem5-specific, SPIs) 320-511: Unused """ # Everything above 2GiB is memory _mem_regions = [ AddrRange('2GB', size='510GB') ] _off_chip_ranges = [ # CS1-CS5 AddrRange(0x0c000000, 0x20000000), # External AXI interface (PCI) AddrRange(0x2f000000, 0x80000000), ] bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), conf_table_reported=False) # NOR flash, flash0 flash0 = SimpleMemory(range=AddrRange(0x08000000, size='64MB'), conf_table_reported=False) # Trusted SRAM trusted_sram = SimpleMemory(range=AddrRange(0x04000000, size='256kB'), conf_table_reported=False) # Platform control device (off-chip) realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, idreg=0x30101100, pio_addr=0x1c010000) mcc = VExpressMCC() dcc = CoreTile2A15DCC() ### On-chip devices ### # Trusted Watchdog, SP805 trusted_watchdog = Sp805(pio_addr=0x2a490000, int_num=56) sys_counter = SystemCounter() generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), int_phys_ns=ArmPPI(num=30), int_virt=ArmPPI(num=27), int_hyp=ArmPPI(num=26)) generic_timer_mem = GenericTimerMem(cnt_control_base=0x2a430000, cnt_read_base=0x2a800000, cnt_ctl_base=0x2a810000, frames=[ GenericTimerFrame(cnt_base=0x2a820000, int_phys=ArmSPI(num=57), int_virt=ArmSPI(num=133)), GenericTimerFrame(cnt_base=0x2a830000, int_phys=ArmSPI(num=58), int_virt=ArmSPI(num=134)) ]) system_watchdog = Sp805(pio_addr=0x2b060000, int_num=130) def _on_chip_devices(self): return [ self.generic_timer_mem, self.trusted_watchdog, self.system_watchdog ] + self.generic_timer_mem.frames def _on_chip_memory(self): memories = [ self.bootmem, self.trusted_sram, self.flash0, ] return memories ### Off-chip devices ### io_voltage = VoltageDomain(voltage="3.3V") clock32KHz = SrcClockDomain(clock="32kHz") clock24MHz = SrcClockDomain(clock="24MHz") uart = [ Pl011(pio_addr=0x1c090000, int_num=37), Pl011(pio_addr=0x1c0a0000, int_num=38, device=Terminal()), Pl011(pio_addr=0x1c0b0000, int_num=39, device=Terminal()), Pl011(pio_addr=0x1c0c0000, int_num=40, device=Terminal()) ] kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) watchdog = Sp805(pio_addr=0x1c0f0000, int_num=32) rtc = PL031(pio_addr=0x1c170000, int_num=36) ### gem5-specific off-chip devices ### pci_host = GenericArmPciHost( conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, pci_pio_base=0x2f000000, pci_mem_base=0x40000000, int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) energy_ctrl = EnergyCtrl(pio_addr=0x10000000) pwr_ctrl = FVPBasePwrCtrl(pio_addr=0x1c100000) vio = [ MmioVirtIO(pio_addr=0x1c130000, pio_size=0x1000, interrupt=ArmSPI(num=74)), MmioVirtIO(pio_addr=0x1c140000, pio_size=0x1000, interrupt=ArmSPI(num=75)), ] # NOR flash, flash1 flash1 = SimpleMemory(range=AddrRange(0x0c000000, 0x10000000), conf_table_reported=False) def _off_chip_devices(self): return [ self.realview_io, self.kmi0, self.kmi1, self.watchdog, self.rtc, self.pci_host, self.energy_ctrl, self.pwr_ctrl, self.clock32KHz, self.clock24MHz, self.vio[0], self.vio[1], ] + self.uart def _off_chip_memory(self): return [ self.flash1, ] def __init__(self, **kwargs): super(VExpress_GEM5_Base, self).__init__(**kwargs) self.clock32KHz.voltage_domain = self.io_voltage self.clock24MHz.voltage_domain = self.io_voltage self.system_watchdog.clk_domain = self.dcc.osc_sys self.watchdog.clk_domain = self.clock32KHz def attachPciDevice(self, device, *args, **kwargs): device.host = self.pci_host self._num_pci_dev += 1 device.pci_bus = 0 device.pci_dev = self._num_pci_dev device.pci_func = 0 self._attach_device(device, *args, **kwargs) def attachSmmu(self, devices, bus): """ Instantiate a single SMMU and attach a group of client devices to it. The devices' dma port is wired to the SMMU and the SMMU's dma port (master) is attached to the bus. In order to make it work, the list of clients shouldn't contain any device part of the _off_chip_devices or _on_chip_devices. This method should be called only once. Parameters: devices (list): List of devices which will be using the SMMU bus (Bus): The bus downstream of the SMMU. Its slave port will receive memory requests from the SMMU, and its master port will forward accesses to the memory mapped devices """ if hasattr(self, 'smmu'): m5.fatal("A SMMU has already been instantiated\n") self.smmu = SMMUv3(reg_map=AddrRange(0x2b400000, size=0x00020000)) self.smmu.master = bus.slave self.smmu.control = bus.master dma_ports = [] for dev in devices: self._attach_device(dev, bus, dma_ports) self.smmu.connect(dev) def setupBootLoader(self, cur_sys, boot_loader): super(VExpress_GEM5_Base, self).setupBootLoader( cur_sys, boot_loader, 0x8000000, 0x80000000) # Setup m5ops. It's technically not a part of the boot # loader, but this is the only place we can configure the # system. cur_sys.m5ops_base = 0x10010000 def generateDeviceTree(self, state): # Generate using standard RealView function dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state)) if len(dt) > 1: raise Exception("System returned too many DT nodes") node = dt[0] node.appendCompatible(["arm,vexpress"]) node.append(FdtPropertyStrings("model", ["V2P-CA15"])) node.append(FdtPropertyWords("arm,hbi", [0x0])) node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) system = self.system.unproxy(self) if system._have_psci: # PSCI functions exposed to the kernel if not system.have_security: raise AssertionError("PSCI requires EL3 (have_security)") psci_node = FdtNode('psci') psci_node.appendCompatible(['arm,psci-1.0', 'arm,psci-0.2', 'arm,psci']) method = 'smc' psci_node.append(FdtPropertyStrings('method', method)) psci_node.append(FdtPropertyWords('cpu_suspend', 0xc4000001)) psci_node.append(FdtPropertyWords('cpu_off', 0x84000002)) psci_node.append(FdtPropertyWords('cpu_on', 0xc4000003)) psci_node.append(FdtPropertyWords('sys_poweroff', 0x84000008)) psci_node.append(FdtPropertyWords('sys_reset', 0x84000009)) node.append(psci_node) yield node
class HiFive(Platform): """HiFive Platform Implementation: This is the base class for SiFive's HiFive board series. It contains the CLINT and PLIC interrupt controllers, Uart and Disk. Implementation details are based on SiFive FU540-C000. https://sifive.cdn.prismic.io/ sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2 1_FU540-C000-v1p3.pdf Setup: The following sections outline the required setup for a RISC-V HiFive platform. See configs/example/riscv/fs_linux.py for example. Driving CLINT: CLINT has an interrupt pin which increments mtime. It can be connected to any interrupt source pin which acts as the RTCCLK pin. An abstract RTC wrapper called RiscvRTC can be used. Attaching PLIC devices: PLIC handles external interrupts. Interrupt PioDevices should inherit from PlicIntDevice (PCI and DMA not yet implemented). It contains a parameter interrupt_id which should be used to call platform->postPciInt(id). All PLIC interrupt devices should be returned by _off_chip_devices(). Calling attachPlic sets up the PLIC interrupt source count. Uart: The HiFive platform also has an uart_int_id. This is because Uart8250 uses postConsoleInt instead of postPciInt. In the future if a Uart that inherits PlicIntDevice is implemented, this can be removed. Disk: See fs_linux.py for setup example. PMAChecker: The PMAChecker will be attached to the MMU of each CPU (which allows them to differ). See fs_linux.py for setup example. """ type = 'HiFive' cxx_header = "dev/riscv/hifive.hh" system = Param.System(Parent.any, "system") # CLINT clint = Param.Clint(Clint(pio_addr=0x2000000), "CLINT") # PLIC plic = Param.Plic(Plic(pio_addr=0xc000000), "PLIC") # Uart uart = Uart8250(pio_addr=0x10000000) # Int source ID to redirect console interrupts to # Set to 0 if using a pci interrupt for Uart instead uart_int_id = Param.Int(0xa, "PLIC Uart interrupt ID") terminal = Terminal() # Dummy param for generating devicetree cpu_count = Param.Int(0, "dummy") def _on_chip_devices(self): """Returns a list of on-chip peripherals """ return [self.clint, self.plic] def _off_chip_devices(self): """Returns a list of off-chip peripherals """ devices = [self.uart] if hasattr(self, "disk"): devices.append(self.disk) return devices def _on_chip_ranges(self): """Returns a list of on-chip peripherals address range """ return [ AddrRange(dev.pio_addr, size=dev.pio_size) for dev in self._on_chip_devices() ] def _off_chip_ranges(self): """Returns a list of off-chip peripherals address range """ return [ AddrRange(dev.pio_addr, size=dev.pio_size) for dev in self._off_chip_devices() ] def attachPlic(self): """Count number of PLIC interrupt sources """ plic_srcs = [self.uart_int_id] for device in self._off_chip_devices(): if hasattr(device, "interrupt_id"): plic_srcs.append(device.interrupt_id) self.plic.n_src = max(plic_srcs) + 1 def attachOnChipIO(self, bus): """Attach on-chip IO devices, needs modification to support DMA and PCI """ for device in self._on_chip_devices(): device.pio = bus.mem_side_ports def attachOffChipIO(self, bus): """Attach off-chip IO devices, needs modification to support DMA and PCI """ for device in self._off_chip_devices(): device.pio = bus.mem_side_ports def generateDeviceTree(self, state): cpus_node = FdtNode("cpus") cpus_node.append(FdtPropertyWords("timebase-frequency", [10000000])) yield cpus_node node = FdtNode("soc") local_state = FdtState(addr_cells=2, size_cells=2) node.append(local_state.addrCellsProperty()) node.append(local_state.sizeCellsProperty()) node.append(FdtProperty("ranges")) node.appendCompatible(["simple-bus"]) for subnode in self.recurseDeviceTree(local_state): node.append(subnode) yield node def annotateCpuDeviceNode(self, cpu, state): cpu.append(FdtPropertyStrings('mmu-type', 'riscv,sv48')) cpu.append(FdtPropertyStrings('status', 'okay')) cpu.append(FdtPropertyStrings('riscv,isa', 'rv64imafdcsu')) cpu.appendCompatible(["riscv"]) int_node = FdtNode("interrupt-controller") int_state = FdtState(interrupt_cells=1) int_node.append(int_state.interruptCellsProperty()) int_node.append(FdtProperty("interrupt-controller")) int_node.appendCompatible("riscv,cpu-intc") cpus = self.system.unproxy(self).cpu phandle = int_state.phandle(cpus[self.cpu_count]) self.cpu_count += 1 int_node.append(FdtPropertyWords("phandle", [phandle])) cpu.append(int_node)
class T1000(Platform): type = 'T1000' cxx_header = "dev/sparc/t1000.hh" system = Param.System(Parent.any, "system") fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) #warn_access="Accessing Clock Unit -- Unimplemented!") fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, ret_data64=0x0000000000000000, update_data=False) #warn_access="Accessing Memory Banks -- Unimplemented!") fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) #warn_access="Accessing JBI -- Unimplemented!") fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, ret_data64=0x0000000000000001, update_data=True) #warn_access="Accessing L2 Cache Banks -- Unimplemented!") fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, ret_data64=0x0000000000000000, update_data=True) #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) #warn_access="Accessing SSI -- Unimplemented!") hterm = Terminal() hvuart = Uart8250(pio_addr=0xfff0c2c000) htod = DumbTOD() pterm = Terminal() puart0 = Uart8250(pio_addr=0x1f10000000) iob = Iob() # Attach I/O devices that are on chip def attachOnChipIO(self, bus): self.iob.pio = bus.master self.htod.pio = bus.master # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): self.hvuart.device = self.hterm self.puart0.device = self.pterm self.fake_clk.pio = bus.master self.fake_membnks.pio = bus.master self.fake_l2_1.pio = bus.master self.fake_l2_2.pio = bus.master self.fake_l2_3.pio = bus.master self.fake_l2_4.pio = bus.master self.fake_l2esr_1.pio = bus.master self.fake_l2esr_2.pio = bus.master self.fake_l2esr_3.pio = bus.master self.fake_l2esr_4.pio = bus.master self.fake_ssi.pio = bus.master self.fake_jbi.pio = bus.master self.puart0.pio = bus.master self.hvuart.pio = bus.master