def _test(): circ = get_mantle_define_circuit(name)(1) assert verilog.compile(circ) == """ module {name}1 (input [0:0] I0, input [0:0] I1, output [0:0] O); coreir_{op} #(.WIDTH=1) {name}1(.in0(I0), .in1(I1), .out(O)); endmodule """.format(name=name, op=op).lstrip() # NOQA circ = get_mantle_define_circuit(name)(2) assert verilog.compile(circ) == """ module {name}2 (input [1:0] I0, input [1:0] I1, output [1:0] O); coreir_{op} #(.WIDTH=2) {name}2(.in0(I0), .in1(I1), .out(O)); endmodule """.format(name=name, op=op).lstrip() # NOQA
def _test(): circ = get_mantle_define_circuit("Shift" + direction)(2, 1) assert verilog.compile(circ) == """ module Shift{direction}2_1 (input [1:0] I, output [1:0] O); coreir_{} #(.WIDTH=2, .SHIFTBITS=1) Shift{direction}2_1(.in(I), .out(O)); endmodule """.format(op, direction=direction).lstrip() circ = get_mantle_define_circuit("Shift" + direction)(4, 2) assert verilog.compile(circ) == """ module Shift{direction}4_2 (input [3:0] I, output [3:0] O); coreir_{} #(.WIDTH=4, .SHIFTBITS=2) Shift{direction}4_2(.in(I), .out(O)); endmodule """.format(op, direction=direction).lstrip()
def test_invert(): Invert1 = mantle.coreir.DefineInvert(1) assert verilog.compile(Invert1) == """ module Invert1 (input I, output O); coreir_not #(.WIDTH=1) Invert1(.in(I), .out(O)); endmodule """.lstrip() Invert2 = mantle.coreir.DefineInvert(2) assert verilog.compile(Invert2) == """ module Invert2 (input [1:0] I, output [1:0] O); coreir_not #(.WIDTH=2) Invert2(.in(I), .out(O)); endmodule """.lstrip()
def test_dff(): main = DefineCircuit('main', 'I', In(Bit), "O", Out(Bit), "CLK", In(Clock)) dff = DFF() wire(main.I, dff.D) wire(dff.Q, main.O) EndCircuit() assert compile(main) == '''\
def _test_dynamic(): circ = get_mantle_define_circuit("DynamicShift" + direction)(2) assert verilog.compile(circ) == """ module DynamicShift{direction}2 (input [1:0] I0, input [1:0] I1, output [1:0] O); coreir_{} #(.WIDTH=2) DynamicShift{direction}2(.in0(I0), .in1(I1), .out(O)); endmodule """.format(dynamic_op, direction=direction).lstrip() # NOQA
def test_dff(): main = DefineCircuit('main', 'I', In(Bit), "O", Out(Bit), "CLK", In(Clock)) dff = SB_DFF() wire(main.I, dff.D) wire(dff.Q, main.O) EndCircuit() print(compile(main)) # compile will wire up the CLK print(repr(main))
def test_dff(): main = m.DefineCircuit('main', 'I', m.In(m.Bit), "O", m.Out(m.Bit), "CLK", m.In(m.Clock)) dff = SB_DFF() m.wire(main.I, dff.D) m.wire(dff.Q, main.O) m.EndCircuit() print(compile(main)) # compile will wire up the CLK print(repr(main))
def test_fdce(): main = DefineCircuit('main', 'I', In(Bit), "O", Out(Bit), "CLK", In(Clock)) dff = FDCE() wire(m.enable(1), dff.CE) wire(0, dff.CLR) wire(main.I, dff.D) wire(dff.Q, main.O) EndCircuit() print(compile(main)) print(repr(main))
def test_not(): n = DefineCircuit("n", "I", In(Bit), "O", Out(Bit)) inst0 = gates.Not() wire(n.I, inst0[1]) wire(inst0[0], n.O) EndCircuit() assert repr(n) == '''\ n = DefineCircuit("n", "I", In(Bit), "O", Out(Bit)) not_inst0 = not() wire(n.I, not_inst0[1]) wire(not_inst0[0], n.O) EndCircuit()''' assert compile(n) == '''\
def test_buf(): buffer = DefineCircuit("buffer", "I", In(Bit), "O", Out(Bit)) inst0 = gates.Buf() wire(buffer.I, inst0[1]) wire(inst0[0], buffer.O) EndCircuit() assert repr(buffer) == '''\ buffer = DefineCircuit("buffer", "I", In(Bit), "O", Out(Bit)) buf_inst0 = buf() wire(buffer.I, buf_inst0[1]) wire(buf_inst0[0], buffer.O) EndCircuit()''' assert compile(buffer) == '''\
def test_nor2(): nor2 = DefineCircuit("nor2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) inst0 = gates.NOr(2) wire(nor2.I0, inst0[1]) wire(nor2.I1, inst0[2]) wire(inst0[0], nor2.O) EndCircuit() assert repr(nor2) == '''\ nor2 = DefineCircuit("nor2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) nor_inst0 = nor() wire(nor2.I0, nor_inst0[1]) wire(nor2.I1, nor_inst0[2]) wire(nor_inst0[0], nor2.O) EndCircuit()''' assert compile(nor2) == '''\
def test_or2(): or2 = DefineCircuit("or2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) inst0 = gates.Or(2) wire(or2.I0, inst0[1]) wire(or2.I1, inst0[2]) wire(inst0[0], or2.O) EndCircuit() assert repr(or2) == '''\ or2 = DefineCircuit("or2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) or_inst0 = or() wire(or2.I0, or_inst0[1]) wire(or2.I1, or_inst0[2]) wire(or_inst0[0], or2.O) EndCircuit()''' assert compile(or2) == '''\
def test_nand2(): NAnd2 = DefineCircuit("NAnd2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) inst0 = gates.NAnd(2) wire(NAnd2.I0, inst0[1]) wire(NAnd2.I1, inst0[2]) wire(inst0[0], NAnd2.O) EndCircuit() assert repr(NAnd2) == '''\ NAnd2 = DefineCircuit("NAnd2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) nand_inst0 = nand() wire(NAnd2.I0, nand_inst0[1]) wire(NAnd2.I1, nand_inst0[2]) wire(nand_inst0[0], NAnd2.O) EndCircuit()''' assert compile(NAnd2) == '''\
def test_and2(): And2 = DefineCircuit("And2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) inst0 = gates.And(2) wire(And2.I0, inst0[1]) wire(And2.I1, inst0[2]) wire(inst0[0], And2.O) EndCircuit() assert repr(And2) == '''\ And2 = DefineCircuit("And2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) and_inst0 = and() wire(And2.I0, and_inst0[1]) wire(And2.I1, and_inst0[2]) wire(and_inst0[0], And2.O) EndCircuit()''' assert compile(And2) == '''\
def test_xor2(): xor2 = DefineCircuit("xor2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) inst0 = gates.XOr(2) wire(xor2.I0, inst0[1]) wire(xor2.I1, inst0[2]) wire(inst0[0], xor2.O) EndCircuit() assert repr(xor2) == '''\ xor2 = DefineCircuit("xor2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit)) xor_inst0 = xor() wire(xor2.I0, xor_inst0[1]) wire(xor2.I1, xor_inst0[2]) wire(xor_inst0[0], xor2.O) EndCircuit()''' assert compile(xor2) == '''\