def test_coreir_wrap(T):
def define_wrap(type_, type_name, in_type):
def sim_wrap(self, value_store, state_store):
input_val = value_store.get_value(getattr(self, "in"))
value_store.set_value(self.out, input_val)
return DeclareCircuit(
f'coreir_wrap{type_name}',
"in", In(in_type), "out", Out(type_),
coreir_genargs = {"type": type_},
coreir_name="wrap",
coreir_lib="coreir",
simulate=sim_wrap
)
foo = DefineCircuit("foo", "r", In(T))
EndCircuit()
top = DefineCircuit("top", "O", Out(Bit))
foo_inst = foo()
wrap = define_wrap(T, "Bit", Bit)()
wire(bit(0), wrap.interface.ports["in"])
wire(wrap.out, foo_inst.r)
wire(bit(0), top.O)
EndCircuit()
with tempfile.TemporaryDirectory() as tempdir:
filename = f"{tempdir}/top"
compile(filename, top, output="coreir")
got = open(f"{filename}.json").read()
expected_filename = f"tests/test_type/test_coreir_wrap_golden_{T}.json"
expected = open(expected_filename).read()
assert got == expected
def test(circuit, func):
icestick = IceStick()
icestick.Clock.on()
icestick.DSR.on()
icestick.CTS.on()
icestick.D1.on()
icestick.D2.on()
icestick.D3.on()
icestick.D4.on()
icestick.D5.on()
main = icestick.main()
finished, error = generate_test(circuit, func)
wire(finished, main.D3)
wire(finished, main.D4)
wire(finished, main.DSR)
wire(error, main.D1)
wire(error, main.D2)
wire(Not()(error), main.D5)
wire(error, main.CTS)
EndCircuit()
return main
def test_const_wire(T, t):
foo = DefineCircuit("foo", "I", In(T))
EndCircuit()
top = DefineCircuit("top", "O", Out(Bit))
foo_inst = foo()
wire(t(0), foo_inst.I)
wire(bit(0), top.O)
EndCircuit()
with tempfile.TemporaryDirectory() as tempdir:
filename = f"{tempdir}/top"
compile(filename, top, output="coreir")
got = open(f"{filename}.json").read()
expected_filename = f"tests/test_type/test_const_wire_golden.json"
expected = open(expected_filename).read()
assert got == expected
def test_print_ir():
And2 = DeclareCircuit('And2', "I0", In(Bit), "I1", In(Bit), "O", Out(Bit))
AndN2 = DefineCircuit("AndN2", "I", In(Array[2, Bit]), "O", Out(Bit) )
and2 = And2()
wire( AndN2.I[0], and2.I0 )
wire( AndN2.I[1], and2.I1 )
wire( and2.O, AndN2.O )
EndCircuit()
main = DefineCircuit("main", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit))
and2 = AndN2()
main.O( and2(array([main.I0, main.I1])) )
EndCircuit()
result = compile(main)
#print(result)
assert result == """\
def test_fdce():
main = DefineCircuit('main', 'I', In(Bit), "O", Out(Bit), "CLK", In(Clock))
dff = FDCE()
wire(m.enable(1), dff.CE)
wire(0, dff.CLR)
wire(main.I, dff.D)
wire(dff.Q, main.O)
EndCircuit()
print(compile(main))
print(repr(main))
icestick.J1[6].rename('I6').input().on()
icestick.J3[0].rename('D0').output().on()
icestick.J3[1].rename('D1').output().on()
main = icestick.main()
WDATA = array([main.I0, main.I1])
WADDR = array([main.I2, main.I3, 0, 0, 0, 0, 0, 0, 0, 0, 0])
RADDR = array([main.I4, main.I5, 0, 0, 0, 0, 0, 0, 0, 0, 0])
WE = main.I6
O = array([main.D0, main.D1])
N = 2
M = 4096 // N
rom = M * [0]
for i in range(M):
rom[i] = i & 0x3
ramb = RAMB(M, N, rom)
#print(ramb.interface)
wire(WE, ramb.WE)
wire(WADDR, ramb.WADDR)
wire(WDATA, ramb.WDATA)
wire(1, ramb.RE)
wire(RADDR, ramb.RADDR)
wire(ramb.RDATA, O)
EndCircuit()