def create_connect_box():
cb = m.DefineCircuit("connect_box",
"operand0", m.In(m.Bits(1)),
"operand1", m.In(m.Bits(1)),
"result", m.Out(m.Bits(1)),
"clk", m.In(m.Clock),
"rst", m.In(m.Reset),
"config_data", m.In(m.Bits(32)),
"config_en", m.In(m.Bit))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
m.wire(cb.config_data, config_reg.I)
m.wire(cb.clk, config_reg.CLK)
m.wire(cb.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], cb.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Operations in CB
and_op = mantle.And(2, 1)
m.wire(cb.operand0, and_op.I0)
m.wire(cb.operand1, and_op.I1)
or_op = mantle.Or(2, 1)
m.wire(cb.operand0, or_op.I0)
m.wire(cb.operand1, or_op.I1)
xor_op = mantle.XOr(2, 1)
m.wire(cb.operand0, xor_op.I0)
m.wire(cb.operand1, xor_op.I1)
not_op = mantle.Invert(1)
m.wire(cb.operand0, not_op.I)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, cb.result)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(and_op.O, config_mux.I0)
m.wire(or_op.O, config_mux.I1)
m.wire(xor_op.O, config_mux.I2)
m.wire(not_op.O, config_mux.I3)
return cb
def definition(io):
# Configuration data
config_reg = mantle.Register(32,
init=0,
has_ce=True,
has_reset=True)
m.wire(io.config_data, config_reg.I)
m.wire(io.clk, config_reg.CLK)
m.wire(io.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], io.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Config mux
config_mux = mantle.Mux(height=8, width=1)
m.wire(config_mux.O, io.out)
m.wire(config_mux.S, config_reg.O[0:3])
m.wire(io.track_0_in, config_mux.I0)
m.wire(io.track_1_in, config_mux.I1)
m.wire(io.track_2_in, config_mux.I2)
m.wire(io.track_3_in, config_mux.I3)
m.wire(io.track_0_out, config_mux.I4)
m.wire(io.track_1_out, config_mux.I5)
m.wire(io.track_2_out, config_mux.I6)
m.wire(io.track_3_out, config_mux.I7)
def create_io1out_pad():
cb = m.DefineCircuit("io1out_pad", "clk", m.In(m.Clock), "rst",
m.In(m.Reset), "config_data", m.In(m.Bits(32)),
"config_addr", m.In(m.Bits(32)), "tile_id",
m.In(m.Bits(16)), "pin_0", m.In(m.Bit), "pin_1",
m.In(m.Bit), "pin_2", m.In(m.Bit), "pin_3",
m.In(m.Bit), "top_pin", m.Out(m.Bits(1)))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
addr_match = mantle.EQ(16)
m.wire(addr_match.I0, cb.config_addr[0:16])
m.wire(addr_match.I1, cb.tile_id)
m.wire(addr_match.O, config_reg.CE)
m.wire(cb.config_data, config_reg.I)
m.wire(cb.clk, config_reg.CLK)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], cb.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, cb.top_pin)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(cb.pin_0, config_mux.I0[0])
m.wire(cb.pin_1, config_mux.I1[0])
m.wire(cb.pin_2, config_mux.I2[0])
m.wire(cb.pin_3, config_mux.I3[0])
m.EndDefine()
return cb
def definition(io):
# Configuration data
config_reg = mantle.Register(32,
init=0,
has_ce=True,
has_reset=True)
m.wire(io.config_data, config_reg.I)
m.wire(io.clk, config_reg.CLK)
m.wire(io.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], io.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Operations in CLB
and_op = mantle.And(2, 1)
m.wire(io.operand0, and_op.I0)
m.wire(io.operand1, and_op.I1)
or_op = mantle.Or(2, 1)
m.wire(io.operand0, or_op.I0)
m.wire(io.operand1, or_op.I1)
xor_op = mantle.XOr(2, 1)
m.wire(io.operand0, xor_op.I0)
m.wire(io.operand1, xor_op.I1)
not_op = mantle.Invert(1)
m.wire(io.operand0, not_op.I)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, io.result)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(and_op.O, config_mux.I0)
m.wire(or_op.O, config_mux.I1)
m.wire(xor_op.O, config_mux.I2)
m.wire(not_op.O, config_mux.I3)
def definition(io):
# Configuration data
config_reg = mantle.Register(32,
init=0,
has_ce=True,
has_reset=True)
m.wire(io.config_data, config_reg.I)
m.wire(io.clk, config_reg.CLK)
m.wire(io.config_en, config_reg.CE)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], io.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# switch muxes
config_offset = 0
for side in range(0, 4):
for track in range(0, 4):
switch_mux = mantle.Mux(height=4, width=1)
m.wire(
switch_mux.O,
getattr(
io, 'side_' + str(side) + '_track_' + str(track) +
'_out'))
m.wire(switch_mux.S,
config_reg.O[config_offset:(config_offset + 2)])
config_offset += 2
for in_side in range(0, 4):
if in_side == side:
m.wire(getattr(switch_mux, "I" + str(in_side)),
io.clb_result)
else:
m.wire(
getattr(switch_mux, "I" + str(in_side)),
getattr(
io, 'side_' + str(in_side) + '_track_' +
str(track) + '_in'))
def create_pe_tile():
pe = m.DefineCircuit(
"pe_tile", "clk", m.In(m.Clock), "rst", m.In(m.Reset), "config_data",
m.In(m.Bits(32)), "config_addr", m.In(m.Bits(32)), "tile_id",
m.In(m.Bits(16)), "side_0_track_0_in", m.In(m.Bits(1)),
"side_0_track_1_in", m.In(m.Bits(1)), "side_0_track_2_in",
m.In(m.Bits(1)), "side_0_track_3_in", m.In(m.Bits(1)),
"side_1_track_0_in", m.In(m.Bits(1)), "side_1_track_1_in",
m.In(m.Bits(1)), "side_1_track_2_in", m.In(m.Bits(1)),
"side_1_track_3_in", m.In(m.Bits(1)), "side_2_track_0_in",
m.In(m.Bits(1)), "side_2_track_1_in", m.In(m.Bits(1)),
"side_2_track_2_in", m.In(m.Bits(1)), "side_2_track_3_in",
m.In(m.Bits(1)), "side_3_track_0_in", m.In(m.Bits(1)),
"side_3_track_1_in", m.In(m.Bits(1)), "side_3_track_2_in",
m.In(m.Bits(1)), "side_3_track_3_in", m.In(m.Bits(1)),
"side_0_track_0_out", m.Out(m.Bits(1)), "side_0_track_1_out",
m.Out(m.Bits(1)), "side_0_track_2_out", m.Out(m.Bits(1)),
"side_0_track_3_out", m.Out(m.Bits(1)), "side_1_track_0_out",
m.Out(m.Bits(1)), "side_1_track_1_out", m.Out(m.Bits(1)),
"side_1_track_2_out", m.Out(m.Bits(1)), "side_1_track_3_out",
m.Out(m.Bits(1)), "side_2_track_0_out", m.Out(m.Bits(1)),
"side_2_track_1_out", m.Out(m.Bits(1)), "side_2_track_2_out",
m.Out(m.Bits(1)), "side_2_track_3_out", m.Out(m.Bits(1)),
"side_3_track_0_out", m.Out(m.Bits(1)), "side_3_track_1_out",
m.Out(m.Bits(1)), "side_3_track_2_out", m.Out(
m.Bits(1)), "side_3_track_3_out", m.Out(m.Bits(1)))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
addr_match = mantle.EQ(16)
m.wire(addr_match.I0, pe.config_addr[0:16])
m.wire(addr_match.I1, pe.tile_id)
m.wire(addr_match.O, config_reg.CE)
m.wire(pe.config_data, config_reg.I)
m.wire(pe.clk, config_reg.CLK)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], pe.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Configure sb = 6, cb0 = 4, cb1 = 5, clb = 7
config_cb0_eq = mantle.EQ(16)
m.wire(m.uint(4, 16), config_cb0_eq.I0)
m.wire(pe.config_addr[16:32], config_cb0_eq.I1)
config_cb1_eq = mantle.EQ(16)
m.wire(m.uint(5, 16), config_cb1_eq.I0)
m.wire(pe.config_addr[16:32], config_cb1_eq.I1)
config_clb_eq = mantle.EQ(16)
m.wire(m.uint(7, 16), config_clb_eq.I0)
m.wire(pe.config_addr[16:32], config_clb_eq.I1)
config_sb_eq = mantle.EQ(16)
m.wire(m.uint(6, 16), config_sb_eq.I0)
m.wire(pe.config_addr[16:32], config_sb_eq.I1)
config_cb0 = mantle.And(2, 1)
m.wire(config_cb0.I0[0], config_cb0_eq.O)
m.wire(config_cb0.I1[0], addr_match.O)
config_cb1 = mantle.And(2, 1)
m.wire(config_cb1.I0[0], config_cb1_eq.O)
m.wire(config_cb1.I1[0], addr_match.O)
config_clb = mantle.And(2, 1)
m.wire(config_clb.I0[0], config_clb_eq.O)
m.wire(config_clb.I1[0], addr_match.O)
config_sb = mantle.And(2, 1)
m.wire(config_sb.I0[0], config_sb_eq.O)
m.wire(config_sb.I1[0], addr_match.O)
# Add ands!
# # CB0
cb0 = create_connect_box(1)()
m.wire(pe.clk, cb0.clk)
m.wire(pe.rst, cb0.rst)
m.wire(pe.config_data, cb0.config_data)
m.wire(config_cb0.O[0], cb0.config_en)
# CB1
cb1 = create_connect_box(1)()
m.wire(pe.clk, cb1.clk)
m.wire(pe.rst, cb1.rst)
m.wire(pe.config_data, cb1.config_data)
m.wire(config_cb1.O[0], cb1.config_en)
# CLB
clb = create_clb(1)()
m.wire(pe.clk, clb.clk)
m.wire(pe.rst, clb.rst)
m.wire(pe.config_data, clb.config_data)
m.wire(config_clb.O[0], clb.config_en)
# Switch box
sb = create_switch_box(1)()
m.wire(pe.clk, sb.clk)
m.wire(pe.rst, sb.rst)
m.wire(pe.config_data, sb.config_data)
m.wire(config_sb.O[0], sb.config_en)
m.wire(clb.result, sb.clb_result)
for side in range(0, 4):
for track in range(0, 4):
m.wire(
getattr(pe,
'side_' + str(side) + '_track_' + str(track) + '_in'),
getattr(sb,
'side_' + str(side) + '_track_' + str(track) + '_in'))
for side in range(0, 4):
for track in range(0, 4):
m.wire(
getattr(pe,
'side_' + str(side) + '_track_' + str(track) + '_out'),
getattr(sb,
'side_' + str(side) + '_track_' + str(track) + '_out'))
# Wiring up CLB, SB and CBs
m.wire(pe.side_0_track_0_in, cb0.track_0_in)
m.wire(pe.side_0_track_1_in, cb0.track_1_in)
m.wire(pe.side_0_track_2_in, cb0.track_2_in)
m.wire(pe.side_0_track_3_in, cb0.track_3_in)
m.wire(sb.side_0_track_0_out, cb0.track_0_out)
m.wire(sb.side_0_track_1_out, cb0.track_1_out)
m.wire(sb.side_0_track_2_out, cb0.track_2_out)
m.wire(sb.side_0_track_3_out, cb0.track_3_out)
m.wire(cb0.out, clb.operand0)
m.wire(pe.side_1_track_0_in, cb1.track_0_in)
m.wire(pe.side_1_track_1_in, cb1.track_1_in)
m.wire(pe.side_1_track_2_in, cb1.track_2_in)
m.wire(pe.side_1_track_3_in, cb1.track_3_in)
m.wire(sb.side_1_track_0_out, cb1.track_0_out)
m.wire(sb.side_1_track_1_out, cb1.track_1_out)
m.wire(sb.side_1_track_2_out, cb1.track_2_out)
m.wire(sb.side_1_track_3_out, cb1.track_3_out)
m.wire(cb1.out, clb.operand1)
m.EndDefine()
return pe