def definition(io):
# Generate the sum
m.wire(XOr(3)(io.I0, io.I1, io.CIN), io.O)
# Generate the carry
m.wire(
Or(3)(And(2)(io.I0, io.I1), And(2)(io.I1, io.CIN),
And(2)(io.I0, io.CIN)), io.COUT)
def Define3to2Op():
Op = DefineCircuit("Op", "I0", In(Bit), "I1", In(Bit), "I2", In(Bit), "O", Out(Bit))
a = And(2)(Op.I0, Op.I1)
b = And(2)(Op.I1, Op.I2)
c = And(2)(Op.I2, Op.I0)
d = Or(3)(a, b, c)
wire(d, Op.O)
EndDefine()
return Op
class FullAdder(m.Circuit):
io = m.IO(I0=m.In(m.Bit),
I1=m.In(m.Bit),
CIN=m.In(m.Bit),
O=m.Out(m.Bit),
COUT=m.Out(m.Bit))
# Generate the sum
m.wire(XOr(3)(io.I0, io.I1, io.CIN), io.O)
# Generate the carry
m.wire(
Or(3)(And(2)(io.I0, io.I1), And(2)(io.I1, io.CIN),
And(2)(io.I0, io.CIN)), io.COUT)
class CounterModM(Circuit):
name = name_
io = IO(**dict(zip(args[::2], args[1::2])))
counter = Counter(n,
cin=cin,
cout=False,
incr=incr,
has_ce=has_ce,
has_reset=True)
reset = Decode(m - 1, n)(counter.O)
if has_reset:
reset = Or(2)(reset, io.RESET)
if has_ce:
CE = io.CE
reset = And(2)(reset, CE)
# reset is sometimes called rollover or RO
# note that we don't return RO in Counter
# should also handle r in the definition
wire(magma.reset(reset), counter.RESET) # synchronous reset
if has_ce:
wire(CE, counter.CE)
if cin:
wire(io.CIN, counter.CIN)
wire(counter.O, io.O)
if cout:
wire(reset, io.COUT)
def debounce(a, slow):
ffa = FF(has_ce=True)
ffa(a, ce=slow)
ffb = FF(has_ce=True)
ffb(ffa.O, ce=slow)
# return the value of a if it is stable for slow duration
return And(2)(ffa.O, ffb.O)
def writeport(addr_width, width, regs, WADDR, I, WE):
n = 1 << addr_width
decoder = Decoder(addr_width)
enable = And(2,n)
enable(decoder(WADDR), repeat(WE, n))
for i in range(n):
regs[i](I, CE=m.enable(enable.O[i]))
def DefineCounterModM(m,
n,
cin=False,
cout=True,
incr=1,
has_ce=False,
has_reset=False):
name = _CounterName(f'Counter{n}_Mod{m}', incr, has_ce, has_reset, cin,
cout)
args = []
if cin:
args += ['CIN', In(Bit)]
args += ["O", Out(UInt(n))]
if cout:
args += ["COUT", Out(Bit)]
args += ClockInterface(has_ce, has_reset)
CounterModM = DefineCircuit(name, *args)
counter = Counter(n,
cin=cin,
cout=False,
incr=incr,
has_ce=has_ce,
has_reset=True)
reset = Decode(m - 1, n)(counter.O)
if has_reset:
reset = Or(2)(reset, CounterModM.RESET)
if has_ce:
CE = CounterModM.CE
reset = And(2)(reset, CE)
# reset is sometimes called rollover or RO
# note that we don't return RO in Counter
# should also handle r in the definition
wire(reset, counter.RESET) # synchronous reset
if has_ce:
wire(CE, counter.CE)
if cin:
wire(CounterModM.CIN, counter.CIN)
wire(counter.O, CounterModM.O)
if cout:
wire(reset, CounterModM.COUT)
EndCircuit()
return CounterModM
def writeport(height, width, regs, WADDR, I, WE):
n = 1 << height
decoder = Decoder(height)
enable = And(2, n)
enable(decoder(WADDR), repeat(WE, n))
for i in range(n):
regs[i](I, CE=enable.O[i])
class HalfAdder(m.Circuit):
io = m.IO(I=m.In(m.Bit),
CIN=m.In(m.Bit),
O=m.Out(m.Bit),
COUT=m.Out(m.Bit))
# Generate the sum
m.wire(XOr(2)(io.I, io.CIN), io.O)
# Generate the carry
m.wire(And(2)(io.I, io.CIN), io.COUT)
def test_bitwise():
check_unary_operator(invert, "Invert", wrapped=False)
check_unary_overloaded_operator(operator.invert, Invert(4))
binary_bits_ops = [
(and_, operator.and_, And(2, 4)),
(or_, operator.or_, Or(2, 4)),
(xor, operator.xor, XOr(2, 4)),
]
for args in binary_bits_ops:
print("Testing {}".format(args))
check_binary_operator(args[0], args[2])
check_binary_overloaded_operator(args[1], args[2])
check_unary_operator(neg, "Negate", wrapped=False)
check_unary_overloaded_operator(operator.neg, Negate(4), T=SInt)
binary_arith_ops = [
(add, operator.add, Add(4, cin=False)),
(sub, operator.sub, Sub(4)),
]
for args in binary_arith_ops:
print("Testing {}".format(args))
check_binary_operator(args[0], args[2], T=Bits)
check_binary_overloaded_operator(args[1], args[2], T=UInt)
check_binary_overloaded_operator(args[1], args[2], T=SInt)
compare_ops = [
# (eq, operator.eq, EQ(4) ),
(lt, operator.lt, ULT(4), SLT(4)),
(le, operator.le, ULE(4), SLE(4)),
(gt, operator.gt, UGT(4), SGT(4)),
(ge, operator.ge, UGE(4), SGE(4))
]
for args in compare_ops:
print("Testing {}".format(args))
check_binary_operator(args[0], args[2], out_type=Bit)
if args[0] == eq:
check_binary_overloaded_operator(args[1], args[2], out_type=Bit)
else:
check_binary_overloaded_operator(args[1],
args[2],
T=UInt,
out_type=Bit)
check_binary_overloaded_operator(args[1],
args[3],
T=SInt,
out_type=Bit)
from magma import wire, compile, EndCircuit
from mantle import And
from loam.boards.icestick import IceStick
N = 2
icestick = IceStick()
for i in range(2 * N):
icestick.J1[i].input().on()
for i in range(N):
icestick.J3[i].output().on()
main = icestick.main()
and2 = And(2, N)
wire(and2(main.J1[0:N], main.J1[N:2 * N]), main.J3)
EndCircuit()
def DefineCounterModM(m,
n,
cin=False,
cout=True,
incr=1,
next=False,
has_ce=False):
r = False
s = False
name = _CounterName('Counter', n, m, has_ce, r, s)
args = []
if cin:
args += ['CIN', In(Bit)]
args += ["O", Out(UInt(n))]
if cout:
args += ["COUT", Out(Bit)]
args += ClockInterface(has_ce, r, s)
CounterModM = DefineCircuit(name, *args)
counter = Counter(n,
cin=cin,
cout=cout,
incr=incr,
next=next,
has_ce=has_ce,
has_reset=True)
reset = Decode(m - 1, n)(counter.O)
if has_ce:
CE = In(Bit)()
reset = And(2)(reset, CE)
# reset is sometimes called rollover or RO
# note that we don't return RO in Counter
# should also handle r in the definition
wire(reset, counter.RESET) # synchronous reset
if has_ce:
wire(CE, counter.CE)
if cin:
wire(CounterModM.CIN, counter.CIN)
wire(counter.O, CounterModM.O)
if cout:
wire(reset, CounterModM.COUT)
wire(CounterModM.CLK, counter.CLK)
if hasattr(counter, "CE"):
wire(CounterModM.CE, counter.CE)
EndCircuit()
return CounterModM
import os
os.environ['MANTLE'] = 'lattice'
from magma import *
from mantle import And, XOr
from simulator import testvectors
main = DefineCircuit('main', "a", In(Bit), "b", In(Bit), "c", In(Bit), "d",
Out(Bit), 'CLK', In(Bit))
t = And(2)(main.a, main.b)
d = XOr(2)(t, main.c)
wire(d, main.d)
EndCircuit()
print(testvectors(main))
def definition(io):
swap = uncurry(fork(And(2), Or(2)), prefix="I")
#swap = uncurry( fork( And(2), Or(2) ) , prefix="in")
wire(swap(io.I), io.O)
def definition(io):
# Generate the sum
m.wire( XOr(2)(io.I, io.CIN), io.O )
# Generate the carry
m.wire( And(2)(io.I, io.CIN), io.COUT )
def and_(*args, **kwargs):
width = get_length(args[0])
return And(len(args), width, **kwargs)(*args)
from magma import wire, compile, EndCircuit
from mantle import And
from loam.boards.icestick import IceStick
icestick = IceStick()
for i in range(2):
icestick.J1[i].input().on()
icestick.D5.on()
main = icestick.main()
and2 = And(2)
and2(main.J1[0], main.J1[1])
wire(and2.O, main.D5)
EndCircuit()