def __init__(self, pads_vga, pads_dvi, lasmim):
pack_factor = lasmim.dw // bpp
g = DataFlowGraph()
self.fi = FrameInitiator(lasmim.aw, pack_factor)
intseq = misc.IntSequence(lasmim.aw, lasmim.aw)
dma_out = AbstractActor(plumbing.Buffer)
g.add_connection(self.fi, intseq, source_subr=self.fi.dma_subr())
g.add_pipeline(intseq, AbstractActor(plumbing.Buffer),
dma_lasmi.Reader(lasmim), dma_out)
cast = structuring.Cast(lasmim.dw,
pixel_layout(pack_factor),
reverse_to=True)
vtg = VTG(pack_factor)
self.driver = Driver(pack_factor, pads_vga, pads_dvi)
g.add_connection(self.fi,
vtg,
source_subr=self.fi.timing_subr,
sink_ep="timing")
g.add_connection(dma_out, cast)
g.add_connection(cast, vtg, sink_ep="pixels")
g.add_connection(vtg, self.driver)
self.submodules += CompositeActor(g)
def __init__(self, bus_accessor, *args, ack_when_inactive=False, **kwargs): bus_aw = flen(bus_accessor.address_data.payload.a) bus_dw = flen(bus_accessor.address_data.payload.d) _DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs) g = DataFlowGraph() adr_buffer = AbstractActor(plumbing.Buffer) int_sequence = misc.IntSequence(bus_aw, bus_aw) g.add_pipeline(self.generator, int_sequence, adr_buffer) g.add_connection(adr_buffer, bus_accessor, sink_subr=["a"]) g.add_connection(AbstractActor(plumbing.Buffer), bus_accessor, sink_subr=["d"]) comp_actor = CompositeActor(g) self.submodules += comp_actor if ack_when_inactive: demultiplexer = plumbing.Demultiplexer(comp_actor.d.payload.layout, 2) self.comb +=[ demultiplexer.sel.eq(~adr_buffer.busy), demultiplexer.source0.connect(comp_actor.d), demultiplexer.source1.ack.eq(1), ] self.submodules += demultiplexer self.data = demultiplexer.sink else: self.data = comp_actor.d self.busy = comp_actor.busy self.comb += self.r_busy.status.eq(self.busy)
def __init__(self, bus_accessor, *args, **kwargs): bus_aw = flen(bus_accessor.address.payload.a) bus_dw = flen(bus_accessor.data.payload.d) _DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs) g = DataFlowGraph() g.add_pipeline(self.generator, misc.IntSequence(bus_aw, bus_aw), AbstractActor(plumbing.Buffer), bus_accessor, AbstractActor(plumbing.Buffer)) comp_actor = CompositeActor(g) self.submodules += comp_actor self.data = comp_actor.q self.busy = comp_actor.busy self.comb += self.r_busy.status.eq(self.busy)
for i in range(10):
v = i + 5
print("==> " + str(v))
yield Token("source", {"maximum": v})
class SimSource(SimActor):
def __init__(self):
self.source = Source([("maximum", 32)])
SimActor.__init__(self, source_gen())
def sink_gen():
while True:
t = Token("sink")
yield t
print(t.value["value"])
class SimSink(SimActor):
def __init__(self):
self.sink = Sink([("value", 32)])
SimActor.__init__(self, sink_gen())
if __name__ == "__main__":
source = SimSource()
loop = misc.IntSequence(32)
sink = SimSink()
g = DataFlowGraph()
g.add_connection(source, loop)
g.add_connection(loop, sink)
comp = CompositeActor(g)
run_simulation(comp, ncycles=500)