def __init__(self, plat):
neopixel_gpio = [('neopixel', 0, Subsignal('tx', Pins('PMOD:0')),
IOStandard('LVCMOS33'))]
plat.add_extension(neopixel_gpio)
neopixel_pads = plat.request('neopixel')
leds = plat.request('user_led')
serial_pads = plat.request('serial')
self.submodules.uart = UART(serial_pads,
baud_rate=115200,
clk_freq=12000000)
self.submodules.restrider = Restrider()
data = Signal(8)
self.submodules.uart_fsm = FSM()
self.uart_fsm.act(
'RX',
If(
self.uart.rx_ready,
self.uart.rx_ack.eq(1),
NextValue(data, self.uart.rx_data),
NextState('INGEST'),
))
self.comb += self.restrider.data_in.eq(data)
self.uart_fsm.act(
'INGEST',
self.restrider.latch_data.eq(1),
NextState('RX'),
)
N_PIXELS = 8
self.submodules.fifo = SyncFIFOBuffered(24, N_PIXELS)
pixel_data = Signal(24)
self.submodules.slurp_fsm = FSM()
self.slurp_fsm.act(
'IDLE', self.fifo.we.eq(0),
If(
self.restrider.done,
self.restrider.out_read_ack.eq(1),
NextValue(pixel_data, self.restrider.data_out),
NextState('CHUNK'),
))
self.comb += self.fifo.din.eq(pixel_data)
self.slurp_fsm.act(
'CHUNK',
If(
self.fifo.writable,
self.fifo.we.eq(1),
),
NextState('IDLE'),
)
self.submodules.neopixels = WS2812Controller(neopixel_pads, self.fifo,
12000000)
self.comb += self.neopixels.write_en.eq(self.fifo.level == N_PIXELS)
def main():
plat = icestick.Platform()
debugpins = [119, 118, 117, 116, 115, 114, 113, 112]
plat.add_extension([
('sio', 0,
Subsignal('rst', Pins('48')),
Subsignal('txd', Pins('56')),
Subsignal('rxd', Pins('60')),
Subsignal('sclk', Pins('61')),
Subsignal('busy', Pins('62')),
Subsignal('tclk', Pins('47')),
IOStandard('LVCMOS33'),
),
] + [
('debug', i, Pins(str(p)), IOStandard('LVCMOS33')) for i, p in enumerate(debugpins)
])
# Randomize seed because it doesn't get routed with the default of 1.
plat.toolchain.pnr_opt = "-q -r"
plat.build(Top(plat))
plat.create_programmer().flash(0, 'build/top.bin')
def __init__(self, plat):
from migen.build.generic_platform import Subsignal, IOStandard, Pins
neopixel_gpio = [
('neopixel', 0,
Subsignal('tx', Pins('PMOD:0')),
IOStandard('LVCMOS33')
)
]
plat.add_extension(neopixel_gpio)
neopixel_pads = plat.request('neopixel')
N_PIXELS = 8
fifo = SyncFIFO(24, N_PIXELS)
self.submodules.controller = WS2812Controller(neopixel_pads, fifo, 12000000)
def mk_extensions(self):
ext_list = None
if self.extensions:
ext_list = []
for name, ext_data in self.extensions.items():
if name not in ("serial", "user_led"):
print("extensions must be one of \"serial\" or \"user_led\"")
exit(2)
ext_count = 0
# Extensions can have more than one instance.
for inst in ext_data:
subsignals = []
pins = []
io_standard = []
pins_cfg = inst.get("pins")
subsig_cfg = inst.get("subsignals")
io_cfg = inst.get("io_standard")
if pins_cfg is not None and subsig_cfg is not None:
print("extensions must contain \"pins\" or \"subsignals\", but not both")
exit(3)
if pins_cfg:
pins.append(Pins(pins_cfg))
if subsig_cfg:
for sub_name, sub_data in subsig_cfg.items():
subsignals.append(Subsignal(sub_name, Pins(sub_data["pins"])))
# io_standard on subsignal not supported yet.
if io_cfg:
io_standard.append(IOStandard(io_cfg))
ext_list.append((name, ext_count, *pins, *subsignals, *io_standard))
ext_count = ext_count + 1
return ext_list
from migen.build.generic_platform import Pins, IOStandard, Subsignal
from migen.build.altera import AlteraPlatform
from migen.build.altera.programmer import USBBlaster
_io = [
("clk1_50", 0, Pins("V11"), IOStandard("3.3-V LVTTL")),
("clk2_50", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
("clk3_50", 0, Pins("E11"), IOStandard("3.3-V LVTTL")),
("user_led", 0, Pins("W15"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("AA24"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("V16"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("V15"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("AF26"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("AE26"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("Y16"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("AA23"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")),
("sw", 0, Pins("L10"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("L9"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("H6"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("H5"), IOStandard("3.3-V LVTTL")),
("epcs", 0, Subsignal("data0",
Pins("AD7")), Subsignal("data1", Pins("AC6")),
Subsignal("data2", Pins("AC5")), Subsignal("data3", Pins("AB6")),
Subsignal("dclk", Pins("AA8")), Subsignal("ncso", Pins("AA6")),
IOStandard("3.3-V LVTTL")),
("adc", 0, Subsignal("convst", Pins("U9")), Subsignal("sck", Pins("V10")),
Subsignal("sdi", Pins("AC4")), Subsignal("sdo", Pins("AD4")),
IOStandard("3.3-V LVTTL")),
("gpio_0", 0,
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0, Subsignal("clk", Pins("B24"), IOStandard("LVCMOS33")),
Subsignal("por_b", Pins("C23"), IOStandard("LVCMOS33")),
Subsignal("srst_b", Pins("A22"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal(
"dq",
Pins(
"J26 F25 J25 G26 H26 H23 J24 J23 K26 L23 M26 K23 M25 N24 M24 N23 "
"R26 P24 N26 P23 T24 T25 T23 R23 V24 U26 U24 U25 W26 Y25 Y26 W23"
), IOStandard("SSTL15_T_DCI")),
Subsignal("dm", Pins("G24 K25 P26 V26"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("G25 L25 R25 W25"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("H24 L24 P25 W24"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal(
"a",
Pins(
"K22 K20 N21 L22 M20 N22 L20 J21 T20 U20 M22 H21 P20 J20 R20"
), IOStandard("SSTL15")),
Subsignal("ba", Pins("U22 T22 R22"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("Y23"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("V21"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("W21"), IOStandard("SSTL15_T_DCI")),
Subsignal("ras_n", Pins("V23"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("V22"), IOStandard("SSTL15")),
Subsignal("odt", Pins("Y22"), IOStandard("SSTL15")),
Subsignal("cke", Pins("U21"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("Y21"), IOStandard("SSTL15")),
Subsignal("clk_n", Pins("P21"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("R21"), IOStandard("DIFF_SSTL15")),
Subsignal("reset_n", Pins("H22"), IOStandard("SSTL15"))),
])
def __init__(self, **kwargs):
super().__init__(**kwargs)
self.add_extension([
(
"ps",
0,
Subsignal(
"clk", Pins("E7"), IOStandard("LVCMOS33")
), # "system clock" block on schematics is powered by 3.3V
Subsignal(
"por_b", Pins("C7"), IOStandard("LVCMOS25")
), # shared with Ethernet reset, and Ethernet is 2.5V on schematics
Subsignal("srst_b", Pins("B10"),
IOStandard("LVCMOS25"))), # pullup to 2.5V near TP3
# SDRAM is undocumented but these pins are fixed on Zynq.
("ddr", 0,
Subsignal("a",
Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15")),
Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15")),
Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
Subsignal("dm", Pins("A1 F1 T1 Y1"), IOStandard("SSTL15_T_DCI")),
Subsignal(
"dq",
Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1 "
"P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("B2 F2 T2 W4"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("C2 G2 R2 W5"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15")),
Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI")),
Subsignal("we_n", Pins("M5"), IOStandard("SSTL15"))),
])
# remove the -l option: auto-promote nets to globals
plat.toolchain.build_template[
1] = "arachne-pnr -r {pnr_pkg_opts} -p {build_name}.pcf {build_name}.blif -o {build_name}.txt"
plat.add_extension([
("debug", 0, Pins("P16 N16 M16 K15")),
("mclk", 0, Pins("R15")),
("wck", 0, Pins("P15")),
("din", 0, Pins("M15")),
("bck", 0, Pins("L16")),
(
"fast_serial",
0,
Subsignal("di", Pins("B10")),
Subsignal("clk", Pins("B12")),
Subsignal("do", Pins("B13")),
Subsignal("cts", Pins("A15")),
IOStandard("LVCMOS33"),
),
])
plat.add_source("pll_test.v")
plat.build(Top(plat))
plat.create_programmer().load_bitstream("build/top.bin")
elif sys.argv[1] == "prog":
from migen.build.platforms import ice40_hx8k_b_evn
plat = ice40_hx8k_b_evn.Platform()
plat.create_programmer().load_bitstream("build/top.bin")
from migen import Module, Signal, Memory
from migen.build.platforms import tinyfpga_bx
from migen.build.generic_platform import Pins, Subsignal, IOStandard
from migen.fhdl import verilog
from migen.fhdl.structure import Mux, Cat, If, Case
import array
plat = tinyfpga_bx.Platform()
plat.add_extension([
("output", 0, Pins("B1 C2 C1 D2 D1 E2 E1 G2"), IOStandard("LVCMOS33")),
("input", 0, Pins("H1 J1 H2 H9 D9 D8 C9 A9"), IOStandard("LVCMOS33")),
])
output = plat.request("output")
dinput = plat.request("input")
# opcode and mode constants.
OP_LD, OP_AND, OP_OR, OP_XOR, OP_ADD, OP_SUB, OP_ST, OP_BCC = range(0,8)
MOD_DAC, MOD_XAC, MOD_YDAC, MOD_YXAC, MOD_DX, MOD_DY, MOD_DOUT, MOD_YXOUT = range(0,8)
MOD_JMP, MOD_BGT, MOD_BLT, MOD_BNE, MOD_BEQ, MOD_BGE, MOD_BLE, MOD_BRA = range(0,8)
with open("gigatron-rom/ROMv3.rom", "rb") as fh:
rom_image = array.array("H", fh.read())
class Gigatron(Module):
def __init__(self):
self.specials.rom = Memory(16, 4096, rom_image)
rom_port = self.rom.get_port(write_capable=False)
from migen.build.lattice import LatticePlatform
from migen.build.lattice.programmer import MyStormProgrammer
_io = [
("sram", 0,
Subsignal("adr", Pins("137 138 139 141 142 42 43 44 73 74 75 76 115",
"116 117 118 119 78")),
Subsignal("dat", Pins("136 135 134 130 125 124 122 121 62 61 60 56 55",
"48 47 45")),
Subsignal("oe", Pins("29")),
Subsignal("we", Pins("120")),
Subsignal("cs", Pins("23")),
Subsignal("ub", Pins("28")),
Subsignal("lb", Pins("24")),
IOStandard("LVCMOS33"),
),
("clk100", 0, Pins("129"), IOStandard("LVCMOS33")),
("mmc", 0,
Subsignal("dat", Pins("63 64 39 38")),
Subsignal("cmd", Pins("41")),
Subsignal("clk", Pins("37")),
IOStandard("LVCMOS33"),
),
("serial", 0,
Subsignal("rx", Pins("88")),
Subsignal("tx", Pins("85")),
Subsignal("rts", Pins("91")),
def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self,
cpu_type="vexriscv",
sdram_controller_type="minicon",
l2_size=128 * 1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
csr_address_width=15,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
platform = self.platform
rtio_clk_freq = 150e6
self.comb += platform.request("input_clk_sel").eq(1)
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean", 0),
data_pads=[platform.request("mch_fabric_d", i) for i in range(11)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtio_csr_group.append(core_name)
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
core = cdr(
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth0 = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth0.txoutclk, rtio_clk_period / 2)
platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth0.txoutclk,
gth0.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth0.txoutclk, gth.rxoutclk)
self.rtio_channels = rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
output_4x = partial(ttl_serdes_ultrascale.Output, 4)
eem.DIO.add_std(self,
2,
output_4x,
output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
eem.Urukul.add_std(self,
0,
1,
output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
eem.Zotino.add_std(self,
3,
output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
workaround_us_lvds_tristate(platform)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri,
enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0, Subsignal("clk", Pins("A22"), IOStandard("LVCMOS18")),
Subsignal("por_b", Pins("D21"), IOStandard("LVCMOS18")),
Subsignal("srst_b", Pins("B19"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal(
"dq",
Pins(
"A25 E25 B27 D25 B25 E26 D26 E27 A29 A27 A30 A28 C28 D30 D28 D29 "
"H27 G27 H28 E28 E30 F28 G30 F30 J29 K27 J30 J28 K30 M29 L30 M30"
), IOStandard("SSTL15_T_DCI")),
Subsignal("dm", Pins("C27 B30 H29 K28"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("B26 B29 F29 L29"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("C26 C29 G29 L28"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal(
"a",
Pins(
"L25 K26 L27 G25 J26 G24 H26 K22 F27 J23 G26 H24 K23 H23 J24"
), IOStandard("SSTL15")),
Subsignal("ba", Pins("M27 M26 M25"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("M24"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("N21"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("M21"), IOStandard("SSTL15_T_DCI")),
Subsignal("ras_n", Pins("N24"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("N23"), IOStandard("SSTL15")),
Subsignal("odt", Pins("L23"), IOStandard("SSTL15")),
Subsignal("cke", Pins("M22"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("N22"), IOStandard("SSTL15")),
Subsignal("clk_n", Pins("J25"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("K25"), IOStandard("DIFF_SSTL15")),
Subsignal("reset_n", Pins("F25"), IOStandard("SSTL15"))),
])
"""
constraint file for the Kicad board available at
https://github.com/hstarmans/firestarter/tree/master/pi_hat
"""
import subprocess
import platform
import shutil
from migen.build.generic_platform import Subsignal, Pins, IOStandard
from migen.build.lattice import LatticePlatform
_io = [
# numbers are for multiple channels, not really used,
# TODO: wrap polygon in one and laser in one
("gpio14", 0, Pins("113"), IOStandard("LVCMOS33")),
("gpio15", 0, Pins("112"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("61"), IOStandard("LVCMOS33")),
("led2", 0, Pins("8"), IOStandard("LVCMOS33")),
("led3", 0, Pins("3"), IOStandard("LVCMOS33")),
("laser0", 0, Pins("134"), IOStandard("LVCMOS33")),
("laser1", 0, Pins("135"), IOStandard("LVCMOS33")),
("photodiode", 0, Pins("137"), IOStandard("LVCMOS33")),
("poly_en", 0, Pins("141"), IOStandard("LVCMOS33")),
("poly_ready", 0, Pins("138"), IOStandard("LVCMOS33")), # not used
("poly_pwm", 0, Pins("139"), IOStandard("LVCMOS33")),
("spi", 0, Subsignal('cs_n', Pins("85")), Subsignal('miso', Pins("87")),
Subsignal('mosi',
Pins("90")), Subsignal('clk',
Pins("79")), IOStandard("LVCMOS33"))
]
_connectors = []
from migen import Module, Signal
from migen.build.lattice import LatticePlatform
from migen.build.generic_platform import Pins, IOStandard, Misc, Subsignal
# Pinouts for various Fomu variants.
_io_evt = [
("serial", 0,
Subsignal("rx", Pins("21")),
Subsignal("tx", Pins("13"), Misc("PULLUP")),
IOStandard("LVCMOS33")
),
("usb", 0,
Subsignal("d_p", Pins("34")),
Subsignal("d_n", Pins("37")),
Subsignal("pullup", Pins("35")),
Subsignal("pulldown", Pins("36")),
IOStandard("LVCMOS33")
),
("touch", 0,
Subsignal("t1", Pins("48"), IOStandard("LVCMOS33")),
Subsignal("t2", Pins("47"), IOStandard("LVCMOS33")),
Subsignal("t3", Pins("46"), IOStandard("LVCMOS33")),
Subsignal("t4", Pins("45"), IOStandard("LVCMOS33")),
),
("pmoda", 0,
Subsignal("p1", Pins("28"), IOStandard("LVCMOS33")),
Subsignal("p2", Pins("27"), IOStandard("LVCMOS33")),
Subsignal("p3", Pins("26"), IOStandard("LVCMOS33")),
Subsignal("p4", Pins("23"), IOStandard("LVCMOS33")),
),
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0,
Subsignal("clk", Pins("F7"), IOStandard("LVCMOS33")),
Subsignal("por_b", Pins("B5"), IOStandard("LVCMOS33")),
Subsignal("srst_b", Pins("C9"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal("a",
Pins("M4 M5 K4 L4 K6 K5 J7 J6 J5 H5 J3 G5 H4 F4 G4"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L7 L6 M6"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("P3"), IOStandard("SSTL15")),
Subsignal("cke", Pins("V3"), IOStandard("SSTL15")),
Subsignal("ck_n", Pins("N5"), IOStandard("DIFF_SSTL15")),
Subsignal("ck_p", Pins("N4"), IOStandard("DIFF_SSTL15")),
Subsignal("cs_n", Pins("P6"), IOStandard("SSTL15")),
Subsignal("dm", Pins("B1 H3 P1 AA2"), IOStandard("SSTL15_T_DCI")),
Subsignal("dq",
Pins("D1 C3 B2 D3 E3 E1 F2 F1 G2 G1 L1 L2 L3 K1 J1 K3 "
"M1 T3 N3 T1 R3 T2 M2 R1 AA3 U1 AA1 U2 W1 Y3 W3 Y1"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n",
Pins("D2 J2 P2 W2"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p",
Pins("C2 H2 N2 V2"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("drst_n", Pins("F3"), IOStandard("SSTL15")),
Subsignal("odt", Pins("P5"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("R5"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("M7"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("N7"), IOStandard("SSTL15_T_DCI")),
Subsignal("we_n", Pins("R4"), IOStandard("SSTL15"))),
])
#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-
from migen import *
from migen.fhdl import *
from migen.build.generic_platform import Pins, IOStandard
from migen.build.platforms import apf51
ios = [("user_led", 0, Pins("J2:15"), IOStandard("LVCMOS33"))]
plat = apf51.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0) # led pin on apf51dev
m = Module()
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)
plat.build(m)
def __init__(self, jdcg_type, **kwargs):
SatelliteBase.__init__(self, 150e6,
identifier_suffix="." + jdcg_type,
**kwargs)
platform = self.platform
self.submodules += RTMUARTForward(platform)
# RTM bitstream upload
slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
self.rtio_channels = rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 0)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 1)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG(
platform, use_rtio_clock=True)
cls = {
"sawg": JDCGSAWG,
"pattern": JDCGPattern,
"syncdds": JDCGSyncDDS
}[jdcg_type]
self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0)
self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1)
self.csr_devices.append("jesd_crg")
self.csr_devices.append("jdcg_0")
self.csr_devices.append("jdcg_1")
self.config["HAS_JDCG"] = None
self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.jdcg_0.sawgs +
self.jdcg_1.sawgs
for phy in sawg.phys)
# FMC-VHDCI-EEM DIOs x 2 (all OUTPUTs)
platform.add_connectors(fmcdio_vhdci_eem.connectors)
output_4x = partial(ttl_serdes_ultrascale.Output, 4)
eem.DIO.add_std(self, 0,
output_4x, output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
eem.DIO.add_std(self, 1,
output_4x, output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
# FMC-DIO-32ch-LVDS-a Direction Control Pins (via shift register) as TTLs x 3
platform.add_extension(fmcdio_vhdci_eem.io)
print("fmcdio_vhdci_eem.[CLK, SER, LATCH] starting at RTIO channel 0x{:06x}"
.format(len(rtio_channels)))
fmcdio_dirctl = platform.request("fmcdio_dirctl", 0)
fmcdio_dirctl_phys = [
ttl_simple.Output(fmcdio_dirctl.clk),
ttl_simple.Output(fmcdio_dirctl.ser),
ttl_simple.Output(fmcdio_dirctl.latch)
]
for phy in fmcdio_dirctl_phys:
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
workaround_us_lvds_tristate(platform)
self.add_rtio(rtio_channels)
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts)
self.csr_devices.append("sysref_sampler")
self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
if jdcg_type == "syncdds":
self.comb += [
self.jdcg_0.coarse_ts.eq(self.rtio_tsc.coarse_ts),
self.jdcg_1.coarse_ts.eq(self.rtio_tsc.coarse_ts),
]
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0, Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33")),
Subsignal("por_b", Pins("C7"), IOStandard("LVCMOS33")),
Subsignal("srst_b", Pins("B10"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal("a",
Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15")),
Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15")),
Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
Subsignal("dm", Pins("A1 F1 T1 Y1"), IOStandard("SSTL15_T_DCI")),
Subsignal(
"dq",
Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1 "
"P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("B2 F2 T2 W4"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("C2 G2 R2 W5"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15")),
Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI")),
Subsignal("we_n", Pins("M5"), IOStandard("SSTL15"))),
])
