def __init__(self, comma, sys_clk_freq, check_period=6e-3):
self.rxdata = Signal(20)
self.restart = Signal()
check_max_val = ceil(check_period*sys_clk_freq)
check_counter = Signal(max=check_max_val+1)
check = Signal()
self.sync += [
check.eq(0),
If(check_counter == 0,
check.eq(1),
check_counter.eq(check_max_val)
).Else(
check_counter.eq(check_counter-1)
)
]
comma_n = ~comma & 0b1111111111
comma_seen_rxclk = Signal()
comma_seen = Signal()
self.specials += MultiReg(comma_seen_rxclk, comma_seen)
comma_seen_reset = PulseSynchronizer("sys", "rx")
self.submodules += comma_seen_reset
self.sync.rx += \
If(comma_seen_reset.o,
comma_seen_rxclk.eq(0)
).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
comma_seen_rxclk.eq(1)
)
self.comb += \
If(check,
If(~comma_seen, self.restart.eq(1)),
comma_seen_reset.i.eq(1)
)
def __init__(self, signal):
self._in = CSRStatus(len(signal))
self.specials += MultiReg(signal, self._in.status)
self.submodules.ev = EventManager()
self.ev.cero = EventSourceProcess()
self.ev.uno = EventSourceProcess()
self.ev.dos = EventSourceProcess()
self.ev.tres = EventSourceProcess()
self.ev.cuatro = EventSourceProcess()
self.ev.cinco = EventSourceProcess()
self.ev.seis = EventSourceProcess()
self.ev.siete = EventSourceProcess()
# self.ev.finalize()
self.comb += [
self.ev.cero.trigger.eq(signal[1]),
self.ev.uno.trigger.eq(signal[0]),
self.ev.dos.trigger.eq(signal[2]),
self.ev.tres.trigger.eq(signal[3]),
self.ev.cuatro.trigger.eq(signal[4]),
self.ev.cinco.trigger.eq(signal[5]),
self.ev.seis.trigger.eq(signal[6]),
self.ev.siete.trigger.eq(signal[7])
]
def __init__(self, pad):
self.rtlink = rtlink.Interface(rtlink.OInterface(2, 2),
rtlink.IInterface(1))
self.overrides = []
self.probes = []
# # #
sensitivity = Signal(2)
sample = Signal()
self.sync.rio += [
sample.eq(0),
If(self.rtlink.o.stb & self.rtlink.o.address[1],
sensitivity.eq(self.rtlink.o.data),
If(self.rtlink.o.address[0], sample.eq(1)))
]
i = Signal()
i_d = Signal()
self.specials += MultiReg(pad, i, "rio_phy")
self.sync.rio_phy += i_d.eq(i)
self.comb += [
self.rtlink.i.stb.eq(sample | (sensitivity[0] & (i & ~i_d))
| (sensitivity[1] & (~i & i_d))),
self.rtlink.i.data.eq(i)
]
self.probes += [i]
def __init__(self, sys_clk_freq):
self.idle = Signal() # i
self.polling = Signal() # o
# # #
# Idle Resynchronization -------------------------------------------------------------------
idle = Signal()
self.specials += MultiReg(self.idle, idle)
# Polling LFPS Detection -------------------------------------------------------------------
burst_cycles = ns_to_cycles(sys_clk_freq, PollingLFPS.burst.t_typ)
repeat_cycles = ns_to_cycles(sys_clk_freq, PollingLFPS.repeat.t_typ)
self.count = count = Signal(max=max(burst_cycles, repeat_cycles))
self.found = found = Signal()
self.submodules.fsm = fsm = FSM(reset_state="TBURST")
fsm.act(
"TBURST",
If(
count == 0,
If(
idle == 0,
NextValue(count, burst_cycles - 1),
).Else(NextValue(count, repeat_cycles - 2 * burst_cycles - 1),
NextState("TREPEAT"))).Else(NextValue(count,
count - 1)),
If(found & (idle == 0), self.polling.eq(1), NextValue(found, 0)),
)
fsm.act(
"TREPEAT", NextValue(count, count - 1),
If((count == 0) | (idle == 0), NextValue(found, (count == 0)),
NextValue(count, burst_cycles - 1), NextState("TBURST")))
def __init__(self, channels):
chan_overrides = [c.overrides for c in channels]
max_chan_overrides = max(len(co) for co in chan_overrides)
max_override_len = max(len(o) for co in chan_overrides for o in co)
self.chan_sel = CSRStorage(bits_for(len(chan_overrides) - 1))
self.override_sel = CSRStorage(bits_for(max_chan_overrides - 1))
self.value = CSR(max_override_len)
# # #
chan_overrides_sys = []
for n_channel, co in enumerate(chan_overrides):
co_sys = []
for n_override, o in enumerate(co):
# We do the clock domain transfer with a simple double-latch.
# Software has to ensure proper timing of any strobe signal etc.
# to avoid problematic glitches.
o_sys = Signal.like(o)
self.specials += MultiReg(o_sys, o, "rio")
self.sync += If(
self.value.re & (self.chan_sel.storage == n_channel)
& (self.override_sel.storage == n_override),
o_sys.eq(self.value.r))
co_sys.append(o_sys)
co_sys += [0] * (max_chan_overrides - len(co))
chan_overrides_sys.append(Array(co_sys)[self.override_sel.storage])
self.comb += self.value.w.eq(
Array(chan_overrides_sys)[self.chan_sel.storage])
def __init__(self, pads):
assert len(pads) >= 4 # at least TDI, TDO, TCK, TMS
self.ri = Record(self.layout)
self.ro = Record(self.layout)
self.roe = Record(self.layout)
self.i = self.ri.raw_bits()
self.o = self.ro.raw_bits()
self.oe = self.roe.raw_bits()
self.xi = Array([self.i[0:8], self.i[8:16]])
self.xo = Array([self.o[0:8], self.o[8:16]])
self.xoe = Array([self.oe[0:8], self.oe[8:16]])
self.tck = self.ro.tck
self.tdi = self.ro.tdi
self.tdo = Signal()
self.tms = self.ro.tms
self.loopback = Signal()
###
self.comb += [
Cat([pad.o for pad in pads]).eq(self.o),
Cat([pad.oe for pad in pads]).eq(self.oe),
If(self.loopback,
self.tdo.eq(self.ro.tdi)).Else(self.tdo.eq(self.ri.tdo))
]
self.specials += [MultiReg(Cat([pad.i for pad in pads]), self.i)]
def __init__(self, dw):
self.sink = stream.Endpoint(core_layout(dw))
self.source = stream.Endpoint(core_layout(dw))
self.value = CSRStorage(16)
# # #
value = Signal(16)
self.specials += MultiReg(self.value.storage, value)
counter = Signal(16)
done = Signal()
self.sync += \
If(self.source.ready,
If(done,
counter.eq(0)
).Elif(self.sink.valid,
counter.eq(counter + 1)
)
)
self.comb += [
done.eq(counter == value),
self.sink.connect(self.source, omit=set(["valid"])),
self.source.valid.eq(self.sink.valid & done)
]
def __init__(self, pads):
self.tck = Signal(reset=1)
self.tms = Signal(reset=1)
self.tdo = Signal(reset=1)
self.tdi = Signal(reset=1)
self.trst_z = Signal(reset=0)
self.trst = Signal(reset=1)
###
self.comb += [
pads.tck_t.oe.eq(1),
pads.tck_t.o.eq(self.tck),
pads.tms_t.oe.eq(1),
pads.tms_t.o.eq(self.tms),
pads.tdi_t.oe.eq(1),
pads.tdi_t.o.eq(self.tdi),
]
self.specials += [
MultiReg(pads.tdo_t.i, self.tdo),
]
if hasattr(pads, "trst_t"):
self.sync += [
pads.trst_t.oe.eq(~self.trst_z),
pads.trst_t.o.eq(~self.trst)
]
def __init__(self, link_layer, rx_clock_domain):
self.aux_word_cnt = CSRStatus(64)
self.aux_zword_cnt = CSRStatus(64)
self.rt_word_cnt = CSRStatus(64)
self.rt_zword_cnt = CSRStatus(64)
self.update_link_stats = CSR()
# # #
aux_word = Signal()
aux_zword = Signal()
rt_word = Signal()
rt_zword = Signal()
sync = getattr(self.sync, rx_clock_domain)
sync += [
aux_word.eq(link_layer.rx_aux_frame_perm),
aux_zword.eq(link_layer.rx_aux_frame_perm
& (link_layer.rx_aux_data == 0)),
rt_word.eq(link_layer.rx_rt_frame_perm),
rt_zword.eq(link_layer.rx_rt_frame_perm
& (link_layer.rx_aux_data == 0))
]
for trigger, csr in [(aux_word, self.aux_word_cnt),
(aux_zword, self.aux_zword_cnt),
(rt_word, self.rt_word_cnt),
(rt_zword, self.rt_zword_cnt)]:
counter = ClockDomainsRenamer(rx_clock_domain)(GrayCounter(64))
decoder = GrayDecoder(64)
self.submodules += counter, decoder
counter.q.attr.add("no_retiming")
self.specials += MultiReg(counter.q, decoder.i)
self.comb += counter.ce.eq(trigger)
self.sync += If(self.update_link_stats.re,
csr.status.eq(decoder.o))
def __init__(self, width, reverse=False):
self.config = Signal(2)
self.i = Signal(width)
self.o = Signal(width)
# # #
config = Signal(2)
# Generators.
self.specials += MultiReg(self.config, config)
prbs7 = PRBS7Generator(width)
prbs15 = PRBS15Generator(width)
prbs31 = PRBS31Generator(width)
self.submodules += prbs7, prbs15, prbs31
# PRBS Selection.
prbs_data = Signal(width)
self.comb += [
If(config == 0b11,
prbs_data.eq(prbs31.o)).Elif(config == 0b10,
prbs_data.eq(prbs15.o)).Else(
prbs_data.eq(prbs7.o))
]
# Optional Bits Reversing.
if reverse:
new_prbs_data = Signal(width)
self.comb += new_prbs_data.eq(prbs_data[::-1])
prbs_data = new_prbs_data
# PRBS / Data Selection.
self.comb += [self.o.eq(self.i), If(config != 0, self.o.eq(prbs_data))]
def add_csr(self):
# Reference phase multiplication factors
for i, multf in enumerate(self.mult_factors):
n = 'mult{}'.format(i + 1)
csr = CSRStorage(len(multf), reset=1, name=n)
setattr(self, n, csr)
self.specials += MultiReg(csr.storage, multf, 'sample')
def __init__(self, rtio_clk_freq):
self.pll_reset = CSRStorage(reset=1)
self.pll_locked = CSRStatus()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
clkfbout = Signal()
clkfbin = Signal()
rtiox4_clk = Signal()
pll_locked = Signal()
self.specials += [
Instance("MMCME2_BASE",
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
i_CLKIN1=ClockSignal("rtio"),
i_RST=self.pll_reset.storage,
o_LOCKED=pll_locked,
p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
),
Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
MultiReg(pll_locked, self.pll_locked.status)
]
def __init__(self, data_width):
self.sink = sink = stream.Endpoint(core_layout(data_width))
self.source = source = stream.Endpoint(core_layout(data_width))
self.value = CSRStorage(16)
# # #
value = Signal(16)
self.specials += MultiReg(self.value.storage, value, "scope")
counter = Signal(16)
done = Signal()
self.sync.scope += \
If(source.ready,
If(done,
counter.eq(0)
).Elif(sink.valid,
counter.eq(counter + 1)
)
)
self.comb += [
done.eq(counter == value),
sink.connect(source, omit={"valid"}),
source.valid.eq(sink.valid & done)
]
def __init__(self, period, width=6, clk=None):
self.clk = Signal() if clk is None else clk
self.value = CSRStatus(32)
# # #
self.clock_domains.cd_fmeter = ClockDomain(reset_less=True)
self.comb += self.cd_fmeter.clk.eq(self.clk)
# Period generation
period_done = Signal()
period_counter = Signal(32)
self.comb += period_done.eq(period_counter == period)
self.sync += \
If(period_done,
period_counter.eq(0),
).Else(
period_counter.eq(period_counter + 1)
)
# Frequency measurement
event_counter = ClockDomainsRenamer("fmeter")(GrayCounter(width))
gray_decoder = GrayDecoder(width)
sampler = _Sampler(width)
self.submodules += event_counter, gray_decoder, sampler
self.specials += MultiReg(event_counter.q, gray_decoder.i)
self.comb += [
event_counter.ce.eq(1),
sampler.latch.eq(period_done),
sampler.i.eq(gray_decoder.o),
self.value.status.eq(sampler.o)
]
def __init__(self, pads, dacs):
self.reset = Signal()
self.dcm_sel = Signal()
self.sink = Sink(bus_layout)
###
self.sink.ack.reset = 1
self.submodules.rg = ResetGen()
# two stage synchronizer for inputs
frame = Signal.like(pads.frame)
trigger = Signal()
arm = Signal()
start = Signal()
soft_trigger = Signal()
self.specials += MultiReg(pads.trigger, trigger)
self.sync += [
frame.eq(pads.frame),
pads.aux.eq(Cat(*(dac.out.aux for dac in dacs)) != 0),
#pads.go2_out.eq(
# Cat(*(dac.out.sink.stb for dac in dacs)) != 0),
#pads.go2_out.eq(pads.go2_in), # loop
#pads.go2_out.eq(0),
]
self.comb += [
self.reset.eq(self.rg.reset),
pads.reset.eq(ResetSignal()),
]
for dac in dacs:
self.sync += [
dac.parser.frame.eq(frame),
dac.out.trigger.eq(arm & (trigger | soft_trigger)),
dac.out.arm.eq(arm),
dac.parser.arm.eq(arm),
dac.parser.start.eq(start),
]
self.sync += [
If(
self.sink.stb,
Case(
self.sink.payload.data,
{
0x00: self.rg.trigger.eq(1),
#0x01: self.rg.trigger.eq(0),
0x02: soft_trigger.eq(1),
0x03: soft_trigger.eq(0),
0x04: arm.eq(1),
0x05: arm.eq(0),
0x06: self.dcm_sel.eq(1),
0x07: self.dcm_sel.eq(0),
0x08: start.eq(1),
0x09: start.eq(0),
}))
]
def __init__(self, fifo, asynchronous=False, auto_flush=True):
_FIFOInterface.__init__(self, fifo.width, fifo.depth)
self.submodules.fifo = fifo
self.dout = fifo.dout
self.re = fifo.re
self.readable = fifo.readable
self.din = fifo.din
self.we = fifo.we
self.writable = fifo.writable
self.flush = Signal(reset=auto_flush)
if asynchronous:
self._flush_s = Signal()
self.specials += MultiReg(self.flush,
self._flush_s,
reset=auto_flush)
else:
self._flush_s = self.flush
self.flushed = Signal()
self.queued = Signal()
self._pending = Signal()
self.sync += [
If(self.flushed, self._pending.eq(0)).Elif(self.readable & self.re,
self._pending.eq(1)),
self.queued.eq(self._flush_s & self._pending)
]
def __init__(self, pins, roi_engine_count=16, res_width=12, count_shift=0):
self.config = rtlink.Interface(
rtlink.OInterface(res_width,
bits_for(4*roi_engine_count-1)))
self.gate_data = rtlink.Interface(
rtlink.OInterface(roi_engine_count),
rtlink.IInterface(1+ROI.count_len(res_width, count_shift),
timestamped=False))
self.submodules.deserializer = deserializer_7series.Deserializer(pins)
self.submodules.frequency_counter = FrequencyCounter()
self.submodules.parser = Parser(res_width)
self.comb += self.parser.cl.eq(self.deserializer.q)
self.roi_engines = [ROI(self.parser.pix, count_shift) for _ in range(roi_engine_count)]
self.submodules += self.roi_engines
self.submodules.synchronizer = Synchronizer(self.roi_engines)
self.submodules.serializer = Serializer(self.synchronizer.update, self.synchronizer.counts,
self.gate_data.i)
for n, roi_engine in enumerate(self.roi_engines):
for offset, target in enumerate([roi_engine.cfg.x0, roi_engine.cfg.y0,
roi_engine.cfg.x1, roi_engine.cfg.y1]):
roi_boundary = Signal.like(target)
roi_boundary.attr.add("no_retiming")
self.sync.rtio += If(self.config.o.stb & (self.config.o.address == 4*n+offset),
roi_boundary.eq(self.config.o.data))
self.specials += MultiReg(roi_boundary, target, "cl")
self.sync.rio += If(self.gate_data.o.stb,
self.serializer.gate.eq(self.gate_data.o.data))
def __init__(self, pads):
self.source = source = stream.Endpoint(eth_phy_description(8))
# # #
converter = stream.StrideConverter(converter_description(2),
converter_description(8))
converter = ResetInserter()(converter)
self.submodules += converter
converter_sink_valid = Signal()
converter_sink_data = Signal(2)
self.specials += [
MultiReg(converter_sink_valid, converter.sink.valid, n=2),
MultiReg(converter_sink_data, converter.sink.data, n=2)
]
crs_dv = Signal()
crs_dv_d = Signal()
rx_data = Signal(2)
self.sync += [
crs_dv.eq(pads.crs_dv),
crs_dv_d.eq(crs_dv),
rx_data.eq(pads.rx_data)
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(crs_dv & (rx_data != 0b00),
converter_sink_valid.eq(1),
converter_sink_data.eq(rx_data),
NextState("RECEIVE")
).Else(
converter.reset.eq(1)
)
)
fsm.act("RECEIVE",
converter_sink_valid.eq(1),
converter_sink_data.eq(rx_data),
# end of frame when 2 consecutives 0 on crs_dv
If(~(crs_dv | crs_dv_d),
converter.sink.last.eq(1),
NextState("IDLE")
)
)
self.comb += converter.source.connect(source)
def __init__(self, width, depth):
_FIFOInterface.__init__(self, width, depth)
###
depth_bits = log2_int(depth, True)
produce = ClockDomainsRenamer("write")(GrayCounter(depth_bits+1))
consume = ClockDomainsRenamer("read")(GrayCounter(depth_bits+1))
self.submodules += produce, consume
self.comb += [
produce.ce.eq(self.writable & self.we),
consume.ce.eq(self.readable & self.re)
]
produce_rdomain = Signal(depth_bits+1)
produce.q.attr.add("no_retiming")
self.specials += MultiReg(produce.q, produce_rdomain, "read")
consume_wdomain = Signal(depth_bits+1)
consume.q.attr.add("no_retiming")
self.specials += MultiReg(consume.q, consume_wdomain, "write")
if depth_bits == 1:
self.comb += self.writable.eq((produce.q[-1] == consume_wdomain[-1])
| (produce.q[-2] == consume_wdomain[-2]))
else:
self.comb += [
self.writable.eq((produce.q[-1] == consume_wdomain[-1])
| (produce.q[-2] == consume_wdomain[-2])
| (produce.q[:-2] != consume_wdomain[:-2]))
]
self.comb += self.readable.eq(consume.q != produce_rdomain)
storage = Memory(self.width, depth)
self.specials += storage
wrport = storage.get_port(write_capable=True, clock_domain="write")
self.specials += wrport
self.comb += [
wrport.adr.eq(produce.q_binary[:-1]),
wrport.dat_w.eq(self.din),
wrport.we.eq(produce.ce)
]
rdport = storage.get_port(clock_domain="read")
self.specials += rdport
self.comb += [
rdport.adr.eq(consume.q_next_binary[:-1]),
self.dout.eq(rdport.dat_r)
]
def __init__(self, width):
self.cl = cl = Signal(28)
self.last_x = CSRStatus(width)
self.last_y = CSRStatus(width)
self.pix = pix = Record([
("x", width),
("y", width),
("a", 8),
("b", 8),
("c", 8),
("stb", 1),
("eop", 1),
])
# # #
last_x = Signal(width)
last_y = Signal(width)
lval = Signal()
fval = Signal()
dval = Signal()
last_lval = Signal()
last_fval = Signal()
self.comb += [
Cat(dval, fval, lval).eq(cl[14:17]),
pix.stb.eq(dval & fval & lval),
pix.eop.eq(~fval & last_fval),
Cat(pix.a, pix.b, pix.c).eq(Cat(cl[i] for i in bitseq))
]
self.sync.cl += [
last_lval.eq(lval),
last_fval.eq(fval),
pix.x.eq(pix.x + 1),
If(~lval, pix.x.eq(0), If(last_lval, last_x.eq(pix.x)),
If(last_fval & last_lval, pix.y.eq(pix.y + 1))),
If(~fval, If(last_fval, last_y.eq(pix.y)), pix.y.eq(0))
]
last_x.attr.add("no_retiming")
last_y.attr.add("no_retiming")
self.specials += [
MultiReg(last_x, self.last_x.status),
MultiReg(last_y, self.last_y.status)
]
def __init__(self, width_or_layout, depth): _FIFOInterface.__init__(self, width_or_layout, depth) ### depth_bits = log2_int(depth, True) produce = RenameClockDomains(GrayCounter(depth_bits+1), "write") consume = RenameClockDomains(GrayCounter(depth_bits+1), "read") self.submodules += produce, consume self.comb += [ produce.ce.eq(self.writable & self.we), consume.ce.eq(self.readable & self.re) ] produce_rdomain = Signal(depth_bits+1) self.specials += [ NoRetiming(produce.q), MultiReg(produce.q, produce_rdomain, "read") ] consume_wdomain = Signal(depth_bits+1) self.specials += [ NoRetiming(consume.q), MultiReg(consume.q, consume_wdomain, "write") ] self.comb += [ self.writable.eq((produce.q[-1] == consume_wdomain[-1]) | (produce.q[-2] == consume_wdomain[-2]) | (produce.q[:-2] != consume_wdomain[:-2])), self.readable.eq(consume.q != produce_rdomain) ] storage = Memory(self.width, depth) self.specials += storage wrport = storage.get_port(write_capable=True, clock_domain="write") self.specials += wrport self.comb += [ wrport.adr.eq(produce.q_binary[:-1]), wrport.dat_w.eq(self.din_bits), wrport.we.eq(produce.ce) ] rdport = storage.get_port(clock_domain="read") self.specials += rdport self.comb += [ rdport.adr.eq(consume.q_next_binary[:-1]), self.dout_bits.eq(rdport.dat_r) ]
def __init__(self, clk_freq, sample_tx_freq, **kwargs):
print("HelloLtc: ", kwargs)
SoCCore.__init__(
self,
clk_freq=clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
integrated_rom_size=0,
integrated_main_ram_size=0,
integrated_sram_size=0,
ident="LTC2175 demonstrator", ident_version=True,
**kwargs
)
p = self.platform
self.submodules.crg = _CRG(p, clk_freq, sample_tx_freq)
# ----------------------------
# Serial to Wishbone bridge
# ----------------------------
self.add_cpu(uart.UARTWishboneBridge(
p.request("serial"),
clk_freq,
baudrate=1152000
))
self.add_wb_master(self.cpu.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
# ----------------------------
# FMC LPC connectivity & LTC LVDS driver
# ----------------------------
# LTCPhy will recover ADC clock and drive `sample` clock domain
p.add_extension(ltc_pads)
self.submodules.lvds = LTCPhy(p, sample_tx_freq)
# ----------------------------
# SPI master
# ----------------------------
spi_pads = p.request("LTC_SPI")
self.submodules.spi = spi.SPIMaster(spi_pads)
# ----------------------------
# Acquisition memory for ADC data
# ----------------------------
mem = Memory(16, 4096)
self.specials += mem
self.submodules.sample_ram = SRAM(mem, read_only=True)
self.register_mem("sample", 0x50000000, self.sample_ram.bus, 4096)
self.submodules.acq = Acquisition([mem])
self.specials += MultiReg(
p.request("user_btn"), self.acq.trigger
)
self.comb += [
p.request("user_led").eq(self.acq.busy),
self.acq.data_ins[0].eq(self.lvds.sample_out),
]
def __init__(self, pads, clk=10.):
self.source = do = Endpoint(bus_layout)
self.busy = Signal()
# t_RDLl_Dv = 50 ns (setup)
# t_RDLh_Di = 0ns (hold)
# t_RDLl_RDLh = 50 ns (redundant, <= r_RDLl_Dv)
# t_RDLh_RXFLh = 25ns (from FT245R) (redundant, <= t_RDLh_RDLl)
# t_RXFLh_RXFLl = 80ns (from FT245R)
# t_RDLh_RDLl = 50ns + t_RXh_RXl (we understand this as a
# conditional addition)
# we read every t_hold + t_precharge + t_setup + 2 cycles
# can only sustain 1MByte/s anyway at full speed USB
# stb implicitly needs to be acked within a read cycle
#clk /= 4 # slow it down
t_latch = int(ceil(50 / clk)) + 2 # t_RDLl_Dv + slave skew
t_drop = t_latch + 2 # slave skew
t_refill = t_drop + int(ceil(50 / clk)) # t_RDLh_RDLl
reading = Signal()
rxfl = Signal()
rd_in = Signal()
# proxy rxfl to slaves, drive rdl
self.comb += [
pads.rdl.eq(~pads.g1_out),
self.busy.eq(~do.stb | do.ack)
]
self.specials += [
MultiReg(pads.rxfl, rxfl),
MultiReg(pads.g1_in, rd_in),
]
self.sync += [
If(
~reading & ~rd_in,
pads.g1_out.eq(~rxfl),
),
do.stb.eq(do.stb & ~do.ack),
timeline(rd_in, [
(0, [reading.eq(1)]),
(t_latch, [do.stb.eq(1),
do.payload.data.eq(pads.data)]),
(t_drop, [pads.g1_out.eq(0)]),
(t_refill, [reading.eq(0)]),
])
]
def __init__(self, platform, rtio_internal_clk, use_sma=True):
self._clock_sel = CSRStorage()
self._pll_reset = CSRStorage(reset=1)
self._pll_locked = CSRStatus()
self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
# 100 MHz when using 125MHz input
self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
platform.add_period_constraint(self.cd_ext_clkout.clk, 5.0)
if use_sma:
ext_clkout = platform.request("user_sma_gpio_p_33")
self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
rtio_external_clk = Signal()
if use_sma:
user_sma_clock = platform.request("user_sma_clock")
platform.add_period_constraint(user_sma_clock.p, 8.0)
self.specials += Instance("IBUFDS",
i_I=user_sma_clock.p,
i_IB=user_sma_clock.n,
o_O=rtio_external_clk)
pll_locked = Signal()
rtio_clk = Signal()
rtiox4_clk = Signal()
ext_clkout_clk = Signal()
self.specials += [
Instance(
"PLLE2_ADV",
p_STARTUP_WAIT="FALSE",
o_LOCKED=pll_locked,
p_REF_JITTER1=0.01,
p_CLKIN1_PERIOD=8.0,
p_CLKIN2_PERIOD=8.0,
i_CLKIN1=rtio_internal_clk,
i_CLKIN2=rtio_external_clk,
# Warning: CLKINSEL=0 means CLKIN2 is selected
i_CLKINSEL=~self._clock_sel.storage,
# VCO @ 1GHz when using 125MHz input
p_CLKFBOUT_MULT=8,
p_DIVCLK_DIVIDE=1,
i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage,
o_CLKFBOUT=rtio_clk,
p_CLKOUT0_DIVIDE=2,
p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=rtiox4_clk,
p_CLKOUT1_DIVIDE=5,
p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=ext_clkout_clk),
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
MultiReg(pll_locked, self._pll_locked.status)
]
def __init__(self):
self.pause = Signal()
self.stop = Signal()
self.delay = Signal()
self.reset = Signal()
# # #
new_lock = Signal()
update = Signal()
stop = Signal()
freeze = Signal()
pause = Signal()
reset = Signal()
# DDRDLLA instance -------------------------------------------------------------------------
_lock = Signal()
delay = Signal()
self.specials += Instance("DDRDLLA",
i_RST=ResetSignal("init"),
i_CLK=ClockSignal("sys2x"),
i_UDDCNTLN=~update,
i_FREEZE=freeze,
o_DDRDEL=delay,
o_LOCK=_lock)
lock = Signal()
lock_d = Signal()
self.specials += MultiReg(_lock, lock, "init")
self.sync.init += lock_d.eq(lock)
self.comb += new_lock.eq(lock & ~lock_d)
# DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
t = 8 # in cycles
self.sync.init += [
# Wait DDRDLLA Lock
timeline(
new_lock,
[
(1 * t, [freeze.eq(1)]), # Freeze DDRDLLA
(2 * t, [stop.eq(1)]), # Stop ECLK domain
(3 * t, [reset.eq(1)]), # Reset ECLK domain
(4 * t, [reset.eq(0)]), # Release ECLK domain reset
(5 * t, [stop.eq(0)]), # Release ECLK domain stop
(6 * t, [freeze.eq(0)]), # Release DDRDLLA freeze
(7 * t, [pause.eq(1)]), # Pause DQSBUFM
(8 * t, [update.eq(1)]), # Update DDRDLLA
(9 * t, [update.eq(0)]), # Release DDRDMMA update
(10 * t, [pause.eq(0)]), # Release DQSBUFM pause
])
]
# ------------------------------------------------------------------------------------------
self.comb += [
self.pause.eq(pause),
self.stop.eq(stop),
self.delay.eq(delay),
self.reset.eq(reset),
]
def __init__(self, sys_clk_freq):
self.rx_reset = Signal()
self.rx_pma_reset_done = Signal()
# DRPCLK must be driven by the system clock
self.drpaddr = Signal(9)
self.drpen = Signal()
self.drpdi = Signal(16)
self.drprdy = Signal()
self.drpdo = Signal(16)
self.drpwe = Signal()
self.enable = Signal()
self.restart = Signal()
self.done = Signal()
# Handle async signals
rx_reset = Signal()
self.sync += self.rx_reset.eq(rx_reset)
self.rx_reset.attr.add("no_retiming")
rx_pma_reset_done = Signal()
self.specials += MultiReg(self.rx_pma_reset_done, rx_pma_reset_done)
drpvalue = Signal(16)
drpmask = Signal()
self.comb += [
self.drpaddr.eq(0x011),
If(drpmask,
self.drpdi.eq(drpvalue & 0xf7ff)).Else(self.drpdi.eq(drpvalue))
]
rx_pma_reset_done_r = Signal()
self.sync += rx_pma_reset_done_r.eq(rx_pma_reset_done)
fsm = FSM()
self.submodules += fsm
fsm.act("WAIT_ENABLE", If(self.enable, NextState("GTRXRESET")))
fsm.act("GTRXRESET", rx_reset.eq(1), NextState("DRP_READ_ISSUE"))
fsm.act("DRP_READ_ISSUE", rx_reset.eq(1), self.drpen.eq(1),
NextState("DRP_READ_WAIT"))
fsm.act(
"DRP_READ_WAIT", rx_reset.eq(1),
If(self.drprdy, NextValue(drpvalue, self.drpdo),
NextState("DRP_MOD_ISSUE")))
fsm.act("DRP_MOD_ISSUE", rx_reset.eq(1), drpmask.eq(1),
self.drpen.eq(1), self.drpwe.eq(1), NextState("DRP_MOD_WAIT"))
fsm.act("DRP_MOD_WAIT", rx_reset.eq(1),
If(self.drprdy, NextState("WAIT_PMARST_FALL")))
fsm.act(
"WAIT_PMARST_FALL",
If(rx_pma_reset_done_r & ~rx_pma_reset_done,
NextState("DRP_RESTORE_ISSUE")))
fsm.act("DRP_RESTORE_ISSUE", self.drpen.eq(1), self.drpwe.eq(1),
NextState("DRP_RESTORE_WAIT"))
fsm.act("DRP_RESTORE_WAIT", If(self.drprdy, NextState("DONE")))
fsm.act("DONE", self.done.eq(1),
If(self.restart, NextState("WAIT_ENABLE")))
def __init__(self):
self.enable = Signal(reset=1)
self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
self.source = source = stream.Endpoint(video_data_layout)
# # #
enable = Signal()
self.specials += MultiReg(self.enable, enable)
# Control Path.
pix = Signal(hbits)
bar = Signal(3)
fsm = FSM(reset_state="IDLE")
fsm = ResetInserter()(fsm)
self.submodules.fsm = fsm
self.comb += fsm.reset.eq(~self.enable)
fsm.act("IDLE",
NextValue(pix, 0),
NextValue(bar, 0),
vtg_sink.ready.eq(1),
If(vtg_sink.valid & vtg_sink.first & (vtg_sink.hcount == 0) & (vtg_sink.vcount == 0),
vtg_sink.ready.eq(0),
NextState("RUN")
)
)
fsm.act("RUN",
vtg_sink.connect(source, keep={"valid", "ready", "last", "de", "hsync", "vsync"}),
If(source.valid & source.ready & source.de,
NextValue(pix, pix + 1),
If(pix == (vtg_sink.hres[3:] -1), # 8 Color Bars.
NextValue(pix, 0),
NextValue(bar, bar + 1)
)
)
)
# Data Path.
color_bar = [
# R G B
[0xff, 0xff, 0xff], # White
[0xff, 0xff, 0x00], # Yellow
[0x00, 0xff, 0xff], # Cyan
[0x00, 0xff, 0x00], # Green
[0xff, 0x00, 0xff], # Purple
[0xff, 0x00, 0x00], # Red
[0x00, 0x00, 0xff], # Blue
[0x00, 0x00, 0x00], # Black
]
cases = {}
for i in range(8):
cases[i] = [
source.r.eq(color_bar[i][0]),
source.g.eq(color_bar[i][1]),
source.b.eq(color_bar[i][2])
]
self.comb += Case(bar, cases)
def add_csr(self):
csr_helper(self, 'channel', self.channel, cdc=True)
csr_helper(self, 'threshold', self.threshold, cdc=True)
csr_helper(self, 'wait_pre', self.wait_pre, cdc=True)
csr_helper(self, 'wait_acq', self.wait_acq, cdc=True)
csr_helper(self, 'wait_post', self.wait_post, cdc=True)
self.trig_count_csr = CSRStatus(32, name='trig_count')
self.specials += MultiReg(self.trig_count, self.trig_count_csr.status)
def __init__(self, pins, out_fifo, in_fifo, period_cyc):
jtag_oe = Signal(len(pins))
jtag_o = Signal(len(pins))
jtag_i = Signal(len(pins))
self.comb += [
Cat(pin.oe for pin in pins).eq(jtag_oe),
Cat(pin.o for pin in pins).eq(jtag_o),
]
self.specials += MultiReg(Cat(pin.i for pin in pins), jtag_i)
timer = Signal(max=period_cyc)
cmd = Signal(8)
self.submodules.fsm = FSM(reset_state="RECV-COMMAND")
self.fsm.act("RECV-COMMAND",
If(out_fifo.readable,
out_fifo.re.eq(1),
NextValue(cmd, out_fifo.dout),
If(out_fifo.dout == CMD_W,
NextValue(timer, period_cyc - 1),
NextState("WAIT")
).Elif(out_fifo.dout == CMD_I,
NextState("INPUT")
).Else(
NextState("RECV-DATA")
)
)
)
self.fsm.act("RECV-DATA",
If(out_fifo.readable,
out_fifo.re.eq(1),
If(cmd == CMD_OE,
NextValue(jtag_oe, out_fifo.dout)
).Elif(cmd == CMD_O,
NextValue(jtag_o, out_fifo.dout)
).Elif(cmd == CMD_L,
NextValue(jtag_o, ~out_fifo.dout & jtag_o)
).Elif(cmd == CMD_H,
NextValue(jtag_o, out_fifo.dout | jtag_o)
),
NextState("RECV-COMMAND")
)
)
self.fsm.act("WAIT",
If(timer == 0,
NextState("RECV-COMMAND")
).Else(
NextValue(timer, timer - 1)
)
)
self.fsm.act("INPUT",
If(in_fifo.writable,
in_fifo.we.eq(1),
in_fifo.din.eq(jtag_i),
NextState("RECV-COMMAND")
)
)
def __init__(self, btn_pin):
# Documentation
self.intro = ModuleDoc("""iCEBreaker Button control.
The three momentary switches on the breakaway PMOD.
""")
# HDL Implementation
self._in = CSRStatus(len(btn_pin))
self.specials += MultiReg(btn_pin, self._in.status)
