def __init__(self, platform,
exec_address=0x40800000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)
# # #
self._wb_slaves = WishboneSlaveManager(0x80000000)
# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
mor1kx.MOR1KX(
platform,
OPTION_RESET_PC=exec_address,
FEATURE_PERFCOUNTERS="ENABLED",
OPTION_PERFCOUNTERS_NUM=7))
# DRAM access
self.wb_sdram = wishbone.Interface()
self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram)
def __init__(self,
platform,
exec_address=0x40400000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)
# # #
self._wb_slaves = []
# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(mor1kx.MOR1KX(
platform, exec_address))
# DRAM access
self.wb_sdram = wishbone.Interface()
self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
def __init__(self,
platform,
clk_freq,
cpu_type="lm32",
cpu_reset_address=0x00000000,
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=16 * 1024,
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_baudrate=115200,
ident="",
with_timer=True):
self.platform = platform
self.clk_freq = clk_freq
self.cpu_type = cpu_type
if integrated_rom_size:
cpu_reset_address = 0
self.cpu_reset_address = cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = WishboneSlaveManager(self.shadow_base)
self.config = dict()
self.csr_devices = [
"uart_phy", "uart", "identifier_mem", "timer0", "tmpu"
]
self._memory_groups = [
] # list of (group_name, (group_member0, group_member1, ...))
self._csr_groups = [
] # list of (group_name, (group_member0, group_member1, ...))
self.interrupt_devices = []
if cpu_type == "lm32":
self.submodules.cpu = lm32.LM32(platform, self.cpu_reset_address)
elif cpu_type == "or1k":
self.submodules.cpu = mor1kx.MOR1KX(
platform, OPTION_RESET_PC=self.cpu_reset_address)
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.submodules.tmpu = tmpu.TMPU(self.cpu.dbus)
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.tmpu.output_bus)
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"],
integrated_sram_size, self.sram.bus)
# Main Ram can be used when no external SDRAM is present, and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.register_mem("csr", self.mem_map["csr"], 4 * 2**csr_address_width,
self.wishbone2csr.wishbone)
if with_uart:
self.submodules.uart_phy = uart.RS232PHY(
platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
self.interrupt_devices.append("uart")
if ident:
self.submodules.identifier = identifier.Identifier(ident)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.config["SOC_PLATFORM"] = platform.name
if with_timer:
self.submodules.timer0 = timer.Timer()
self.interrupt_devices.append("timer0")