def __init__(self, rtio_clk_freq=150e6, **kwargs):
BaseSoC.__init__(self, cpu_type="or1k", **kwargs)
add_identifier(self)
platform = self.platform
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("cdr_clk_clean")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p,
i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
if self.hw_rev == "v1.0":
drtio_data_pads = platform.request("sata", 0)
elif self.hw_rev == "v2.0":
drtio_data_pads = platform.request("rtm_amc_link", 0)
else:
raise NotImplementedError
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[drtio_data_pads],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(
DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[0],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
coreaux = cdr(DRTIOAuxController(core.link_layer))
self.submodules.drtioaux0 = coreaux
self.csr_devices.append("drtioaux0")
memory_address = self.mem_map["drtioaux"]
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region("drtioaux0_mem",
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"])
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.cd_sys.clk,
ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9 / rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, rtio_clk_freq, *, with_wrpll, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
**kwargs)
add_identifier(self)
self.rtio_clk_freq = rtio_clk_freq
platform = self.platform
disable_cdrclkc_ibuf = Signal(reset=1)
disable_cdrclkc_ibuf.attr.add("no_retiming")
cdrclkc_clkout = platform.request("cdr_clk_clean")
cdrclkc_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_cdrclkc_ibuf,
i_I=cdrclkc_clkout.p, i_IB=cdrclkc_clkout.n,
o_O=cdrclkc_clkout_buf)
qpll_drtio_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(cdrclkc_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("rtm_amc_link", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_cdrclkc_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[0],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
coreaux = cdr(DRTIOAuxController(core.link_layer))
self.submodules.drtioaux0 = coreaux
self.csr_devices.append("drtioaux0")
memory_address = self.mem_map["drtioaux"]
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"])
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
gtp = self.drtio_transceiver.gtps[0]
rtio_clk_period = 1e9/rtio_clk_freq
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if with_wrpll:
self.comb += [
platform.request("filtered_clk_sel").eq(0),
platform.request("ddmtd_main_dcxo_oe").eq(1),
platform.request("ddmtd_helper_dcxo_oe").eq(1)
]
self.submodules.wrpll_sampler = DDMTDSamplerGTP(
self.drtio_transceiver,
platform.request("cdr_clk_clean_fabric"))
self.submodules.wrpll = WRPLL(
helper_clk_pads=platform.request("ddmtd_helper_clk"),
main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
ddmtd_inputs=self.wrpll_sampler)
self.csr_devices.append("wrpll")
platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
platform.add_false_path_constraints(self.wrpll.cd_helper.clk, gtp.rxoutclk)
else:
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.cd_sys.clk, ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, rtio_clk_freq=150e6, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
**kwargs)
add_identifier(self)
platform = self.platform
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("cdr_clk_clean")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
if self.hw_rev == "v1.0":
drtio_data_pads = platform.request("sata", 0)
elif self.hw_rev == "v2.0":
drtio_data_pads = platform.request("rtm_amc_link", 0)
else:
raise NotImplementedError
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[drtio_data_pads],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[0],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
coreaux = cdr(DRTIOAuxController(core.link_layer))
self.submodules.drtioaux0 = coreaux
self.csr_devices.append("drtioaux0")
memory_address = self.mem_map["drtioaux"]
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"])
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.cd_sys.clk, ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)