def test_vgasys(args=None):
if args is None:
args = Namespace()
res = (80,60)
line_rate = 4000
refresh_rate = 60
else:
# @todo: retrieve these from ...
res = args.res
refresh_rate = args.refresh_rate
line_rate = args.line_rate
clock = Clock(0, frequency=1e6)
reset = Reset(0, active=0, async=False)
vselect = Signal(bool(0))
vga = VGA(color_depth=(10,10,10), )
def _test():
# top-level VGA system
tbdut = mm_vgasys(clock, reset, vselect,
vga.hsync, vga.vsync,
vga.red, vga.green, vga.blue,
vga.pxlen, vga.active,
resolution=res,
refresh_rate=refresh_rate,
line_rate=line_rate)
# group global signals
glbl = Global(clock=clock, reset=reset)
# a display for each dut
mvd = VideoDisplay(frequency=clock.frequency,
resolution=res,
refresh_rate=refresh_rate,
line_rate=line_rate)
# connect VideoDisplay model to the VGA signals
tbvd = mvd.process(glbl, vga)
# clock generator
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(18)
reset.next = not reset.active
# Wait till a full screen has been updated
while mvd.update_cnt < 1:
yield delay(1000)
# @todo: verify video system memory is correct!
# (self checking!)
raise StopSimulation
return tbclk, tbvd, tbstim, tbdut
vcd = tb_clean_vcd('_test')
traceSignals.timescale = '1ns'
traceSignals.name = vcd
Simulation(traceSignals(_test)).run()
convert()
def test_vgasys_conversion():
convert()
# Wait till a full screen has been updated
while mvd.update_cnt < 3:
yield delay(1000)
print("display updates complete")
time.sleep(1)
# @todo: verify video system memory is correct!
# @todo: (self checking!). Read one of the frame
# @todo: png's and verify a couple bars are expected
raise StopSimulation
return tbclk, tbvd, tbstim, tbdut
# run the verification simulation
run_testbench(bench_vgasys)
@skip_long_sim_test
def test_vgasys_conversion():
convert()
if __name__ == '__main__':
args = Namespace(resolution=(80, 60),
color_depth=(10, 10, 10),
line_rate=4000,
refresh_rate=60)
tb_vgasys(args)
convert()
def test_vgasys_conversion():
convert()
# Wait till a full screen has been updated
while mvd.update_cnt < 3:
yield delay(1000)
print("display updates complete")
time.sleep(1)
# @todo: verify video system memory is correct!
# @todo: (self checking!). Read one of the frame
# @todo: png's and verify a couple bars are expected
raise StopSimulation
return tbclk, tbvd, tbstim, tbdut
# run the verification simulation
run_testbench(_bench_vgasys)
def test_vgasys_conversion():
convert()
if __name__ == '__main__':
args = Namespace(resolution=(80, 60),
color_depth=(10, 10, 10),
line_rate=4000,
refresh_rate=60)
tb_vgasys(args)
convert()
def test_vgasys(args=None):
if args is None:
args = Namespace()
res = (80, 60)
line_rate = 4000
refresh_rate = 60
else:
# @todo: retrieve these from ...
res = args.res
refresh_rate = args.refresh_rate
line_rate = args.line_rate
clock = Clock(0, frequency=1e6)
reset = Reset(0, active=0, async=False)
vselect = Signal(bool(0))
vga = VGA(color_depth=(10, 10, 10), )
def _test():
# top-level VGA system
tbdut = mm_vgasys(clock,
reset,
vselect,
vga.hsync,
vga.vsync,
vga.red,
vga.green,
vga.blue,
vga.pxlen,
vga.active,
resolution=res,
refresh_rate=refresh_rate,
line_rate=line_rate)
# group global signals
glbl = Global(clock=clock, reset=reset)
# a display for each dut
mvd = VideoDisplay(frequency=clock.frequency,
resolution=res,
refresh_rate=refresh_rate,
line_rate=line_rate)
# connect VideoDisplay model to the VGA signals
tbvd = mvd.process(glbl, vga)
# clock generator
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(18)
reset.next = not reset.active
# Wait till a full screen has been updated
while mvd.update_cnt < 1:
yield delay(1000)
# @todo: verify video system memory is correct!
# (self checking!)
raise StopSimulation
return tbclk, tbvd, tbstim, tbdut
vcd = tb_clean_vcd('_test')
traceSignals.timescale = '1ns'
traceSignals.name = vcd
Simulation(traceSignals(_test)).run()
convert()
