Example #1
0
def generatePrj(moduleList, module, globalVerilogs, globalVHDs):
    # spit out a new top-level prj
    prjPath = 'config/' + module.wrapperName() + '.prj' 
    newPRJFile = open(prjPath, 'w') 
 
    # Emit verilog source and stub references
    verilogs = globalVerilogs + [model.get_temp_path(moduleList,module) + module.wrapperName() + '.v']
    verilogs +=  moduleList.getDependencies(module, 'VERILOG_STUB')
    for vlog in sorted(verilogs):
        # ignore system verilog files.  XST can't compile them anyway...
        if (not re.search('\.sv\s*$',vlog)):    
            newPRJFile.write("verilog work " + vlog + "\n")
    for vhd in sorted(globalVHDs):
        newPRJFile.write("vhdl work " + vhd + "\n")

    newPRJFile.close()
    return prjPath
Example #2
0
def generatePrj(moduleList, module, globalVerilogs, globalVHDs):
    # spit out a new top-level prj
    prjPath = 'config/' + module.wrapperName() + '.prj' 
    newPRJFile = open(prjPath, 'w') 
 
    # Emit verilog source and stub references
    verilogs = globalVerilogs + [model.get_temp_path(moduleList,module) + module.wrapperName() + '.v']
    verilogs +=  moduleList.getDependencies(module, 'VERILOG_STUB')
    for vlog in sorted(verilogs):
        # ignore system verilog files.  XST can't compile them anyway...
        if (not re.search('\.sv\s*$',vlog)):    
            newPRJFile.write("verilog work " + vlog + "\n")
    for vhd in sorted(globalVHDs):
        newPRJFile.write("vhdl work " + vhd + "\n")

    newPRJFile.close()
    return prjPath
Example #3
0
def buildVivadoEDF(moduleList, module, globalVerilogs, globalVHDs):

    compile_dir = moduleList.env.Dir(moduleList.compileDirectory)
    vivadoCompileDirectory = compile_dir.Dir(module.wrapperName() + '_synth/')

    if not os.path.isdir(str(vivadoCompileDirectory)):
       os.mkdir(str(vivadoCompileDirectory))

    #Let's synthesize a xilinx .prj file for this synth boundary.
    # spit out a new prj
    tclDeps = generateVivadoTcl(moduleList, module, globalVerilogs, globalVHDs, vivadoCompileDirectory)

    checkpointFile = vivadoCompileDirectory.File(module.wrapperName() + '.synth.dcp')
    edfFile = vivadoCompileDirectory.File(module.wrapperName() + '.edf')
    srpFile = vivadoCompileDirectory.File(module.wrapperName() + '.synth.opt.util')
    logFile = module.wrapperName() + '.synth.log'
    resourceFile = vivadoCompileDirectory.File(module.wrapperName() + '.resources')

    # area group modules have a different base dependency than normal
    # modules
    wrapperVerilogDependency = model.get_temp_path(moduleList,module) + module.wrapperName() + '_stub.v'
    if(not module.getAttribute('AREA_GROUP') is None):
        # grab the parent stub?          
        wrapperVerilogDependency = model.get_temp_path(moduleList,module) + module.wrapperName() + '.v'

    # Sort dependencies because SCons will rebuild if the order changes.
    sub_netlist = moduleList.env.Command(
        [edfFile, srpFile, checkpointFile],
        [wrapperVerilogDependency] +
        sorted(moduleList.getDependencies(module,'VERILOG')) +
        tclDeps + 
        sorted(moduleList.getAllDependencies('VERILOG_LIB')) +
        sorted(model.convertDependencies(moduleList.getDependencies(module, 'VERILOG_STUB'))),
        [ SCons.Script.Delete(vivadoCompileDirectory.File(module.wrapperName() + '.synth.opt.util')),
          SCons.Script.Delete(vivadoCompileDirectory.File(module.wrapperName() + '_xst.xrpt')),
          'cd ' + vivadoCompileDirectory.path + '; touch start.txt; vivado -nojournal -mode batch -source ' + module.wrapperName() + '.synthesis.tcl 2>&1 > ' + logFile,
          '@echo vivado synthesis ' + module.wrapperName() + ' build complete.' ])

    utilFile = moduleList.env.Command(resourceFile,
                                      srpFile,
                                      getVivadoUtilResourcesClosure(module))

    module.moduleDependency['SRP'] = [srpFile]

    if (not 'GEN_NGCS' in module.moduleDependency):
        module.moduleDependency['GEN_NGCS'] = [edfFile]
    else:
        module.moduleDependency['GEN_NGCS'] += [edfFile]

    module.moduleDependency['GEN_VIVADO_DCPS'] = [checkpointFile]

    module.moduleDependency['RESOURCES'] = [utilFile]

    module.moduleDependency['SYNTHESIS'] = [edfFile]
    SCons.Script.Clean(sub_netlist,  compile_dir.File(module.wrapperName() + '.srp'))

    # If we're building for the FPGA, we'll claim that the
    # top-level build depends on the existence of the ngc
    # file. This allows us to do resource analysis later on.
    if(moduleList.getAWBParam('bsv_tool', 'BUILD_LOGS_ONLY')):
        moduleList.topDependency += [utilFile]      

    return sub_netlist
Example #4
0
def generateVivadoTcl(moduleList, module, globalVerilogs, globalVHDs, vivadoCompileDirectory):
    # spit out a new top-level prj
    prjPath = vivadoCompileDirectory.File(module.wrapperName() + '.synthesis.tcl')
    newTclFile = open(str(prjPath), 'w') 
 
    # Emit verilog source and stub references
    verilogs = globalVerilogs + [model.get_temp_path(moduleList,module) + module.wrapperName() + '.v']
    verilogs +=  moduleList.getDependencies(module, 'VERILOG_STUB')

    givenNetlists = [ moduleList.env['DEFS']['ROOT_DIR_HW'] + '/' + netlist for netlist in moduleList.getAllDependenciesWithPaths('GIVEN_NGCS') + moduleList.getAllDependenciesWithPaths('GIVEN_EDFS') ]

    # Replace any known black boxes
    blackBoxDeps = []
    blackBoxes = module.getAttribute('BLACK_BOX')
    for vlog in sorted(verilogs):
        if(not blackBoxes is None):
            if(vlog in blackBoxes):
                vlog = blackBoxes[vlog]
                blackBoxDeps.append(vlog)
        relpath = model.rel_if_not_abspath(vlog, str(vivadoCompileDirectory))
        newTclFile.write("read_verilog -quiet " + relpath + "\n")
       
    # grab the system verilogs. 
    for sysv in map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths('GIVEN_SYSTEM_VERILOGS')):
        relpath = model.rel_if_not_abspath(sysv, str(vivadoCompileDirectory))
        newTclFile.write("read_verilog -sv -quiet " + relpath + "\n")
    
    for vhd in sorted(globalVHDs):
        if(isinstance(vhd, model.Source.Source)):            
            # Got a source object, potentially more work to do.
            relpath = model.rel_if_not_abspath(vhd.file, str(vivadoCompileDirectory))
            lib = 'work'
            if('lib' in vhd.attributes):
                newTclFile.write("read_vhdl -lib " + vhd.attributes['lib'] + " " + relpath + "\n")
        else:
            # Just got a string
            relpath = model.rel_if_not_abspath(vhd, str(vivadoCompileDirectory))
            newTclFile.write("read_vhdl -lib work " + relpath + "\n")

    for netlist in givenNetlists:
        relpath = model.rel_if_not_abspath(netlist, str(vivadoCompileDirectory))
        newTclFile.write('read_edif ' + relpath + '\n')

    annotationFiles, annotationDeps = generateSynthesisTcl(moduleList, module, vivadoCompileDirectory)

    part = moduleList.getAWBParam('physical_platform_config', 'FPGA_PART_XILINX')
    
    # the out of context option instructs the tool not to place iobuf
    # and friends on the external ports.
 
    # First, elaborate the rtl design. 

    inc_dirs = model.rel_if_not_abspath(moduleList.env['DEFS']['ROOT_DIR_HW_INC'], str(vivadoCompileDirectory))

    # For the top module, we don't use out of context.b
    if(module.getAttribute('TOP_MODULE') is None):
        newTclFile.write("synth_design -rtl -mode out_of_context -top " + module.wrapperName() + " -part " + part + " -include_dirs " + inc_dirs + "\n")
    else:
        newTclFile.write("synth_design -rtl -top " + module.wrapperName() + " -part " + part + " -include_dirs " + inc_dirs + "\n")


    for file in annotationFiles:
        newTclFile.write("add_files " + file + "\n")
        if(module.getAttribute('TOP_MODULE') is None):
            newTclFile.write("set_property USED_IN {synthesis implementation out_of_context} [get_files " + file + "]\n")
        else:
            newTclFile.write("set_property USED_IN {synthesis implementation} [get_files " + file + "]\n")

    if(module.getAttribute('TOP_MODULE') is None):
        clockConversion = ""
        useClockConversion = moduleList.getAWBParamSafe('synthesis_tool', 'VIVADO_ENABLE_CLOCK_CONVERSION')
        print " VIVADO CLOCK CONVERSION: " + str(useClockConversion)
        if(useClockConversion > 0):
            clockConversion = " -gated_clock_conversion auto "
        
        newTclFile.write("synth_design  " + clockConversion + " -mode out_of_context -top " + module.wrapperName() + " -part " + part + " -include_dirs " + inc_dirs + "\n")

        newTclFile.write("set_property HD.PARTITION 1 [current_design]\n")
    else:
        newTclFile.write("synth_design -top " + module.wrapperName() + " -part " + part + " -include_dirs " + inc_dirs + "\n")

    newTclFile.write("all_clocks\n")
    newTclFile.write("report_clocks\n")
    newTclFile.write("report_utilization -file " + module.wrapperName() + ".synth.preopt.util\n")
    

    # We should do opt_design here because it will be faster in
    # parallel.  However, opt_design seems to cause downstream
    # problems and needs more testing. 
   
    newTclFile.write("opt_design -quiet\n")

    newTclFile.write("report_utilization -file " + module.wrapperName() + ".synth.opt.util\n")
    newTclFile.write("write_checkpoint -force " + module.wrapperName() + ".synth.dcp\n")
    newTclFile.write("close_project -quiet\n")
    newTclFile.close()
    return [prjPath] + blackBoxDeps + annotationDeps
Example #5
0
def buildVivadoEDF(moduleList, module, globalVerilogs, globalVHDs):

    compile_dir = moduleList.env.Dir(moduleList.compileDirectory)
    vivadoCompileDirectory = compile_dir.Dir(module.wrapperName() + '_synth/')

    if not os.path.isdir(str(vivadoCompileDirectory)):
       os.mkdir(str(vivadoCompileDirectory))

    #Let's synthesize a xilinx .prj file for this synth boundary.
    # spit out a new prj
    tclDeps = generateVivadoTcl(moduleList, module, globalVerilogs, globalVHDs, vivadoCompileDirectory)

    checkpointFile = vivadoCompileDirectory.File(module.wrapperName() + '.synth.dcp')
    edfFile = vivadoCompileDirectory.File(module.wrapperName() + '.edf')
    srpFile = vivadoCompileDirectory.File(module.wrapperName() + '.synth.opt.util')
    logFile = module.wrapperName() + '.synth.log'
    resourceFile = vivadoCompileDirectory.File(module.wrapperName() + '.resources')

    # area group modules have a different base dependency than normal
    # modules
    wrapperVerilogDependency = model.get_temp_path(moduleList,module) + module.wrapperName() + '_stub.v'
    if(not module.getAttribute('AREA_GROUP') is None):
        # grab the parent stub?          
        wrapperVerilogDependency = model.get_temp_path(moduleList,module) + module.wrapperName() + '.v'

    # Sort dependencies because SCons will rebuild if the order changes.
    sub_netlist = moduleList.env.Command(
        [edfFile, srpFile, checkpointFile],
        [wrapperVerilogDependency] +
        sorted(moduleList.getDependencies(module,'VERILOG')) +
        tclDeps + 
        sorted(moduleList.getAllDependencies('VERILOG_LIB')) +
        sorted(map(model.modify_path_hw,moduleList.getAllDependenciesWithPaths('GIVEN_VERILOGS'))) +
        sorted(model.convertDependencies(moduleList.getDependencies(module, 'VERILOG_STUB'))),
        [ SCons.Script.Delete(vivadoCompileDirectory.File(module.wrapperName() + '.synth.opt.util')),
          SCons.Script.Delete(vivadoCompileDirectory.File(module.wrapperName() + '_xst.xrpt')),
          'cd ' + vivadoCompileDirectory.path + '; touch start.txt; vivado -nojournal -mode batch -source ' + module.wrapperName() + '.synthesis.tcl 2>&1 > ' + logFile,
          '@echo vivado synthesis ' + module.wrapperName() + ' build complete.' ])

    utilFile = moduleList.env.Command(resourceFile,
                                      srpFile,
                                      getVivadoUtilResourcesClosure(module))

    module.moduleDependency['SRP'] = [srpFile]

    if (not 'GEN_NGCS' in module.moduleDependency):
        module.moduleDependency['GEN_NGCS'] = [edfFile]
    else:
        module.moduleDependency['GEN_NGCS'] += [edfFile]

    module.moduleDependency['GEN_VIVADO_DCPS'] = [checkpointFile]

    module.moduleDependency['RESOURCES'] = [utilFile]

    module.moduleDependency['SYNTHESIS'] = [edfFile]
    SCons.Script.Clean(sub_netlist,  compile_dir.File(module.wrapperName() + '.srp'))

    # If we're building for the FPGA, we'll claim that the
    # top-level build depends on the existence of the ngc
    # file. This allows us to do resource analysis later on.
    if(moduleList.getAWBParam('bsv_tool', 'BUILD_LOGS_ONLY')):
        moduleList.topDependency += [utilFile]      

    return sub_netlist
Example #6
0
def generateVivadoTcl(moduleList, module, globalVerilogs, globalVHDs, vivadoCompileDirectory):
    # spit out a new top-level prj
    prjPath = vivadoCompileDirectory.File(module.wrapperName() + '.synthesis.tcl')
    newTclFile = open(str(prjPath), 'w') 
 
    # Emit verilog source and stub references
    verilogs = globalVerilogs + [model.get_temp_path(moduleList,module) + module.wrapperName() + '.v']
    verilogs +=  moduleList.getDependencies(module, 'VERILOG_STUB')

    givenNetlists = [ moduleList.env['DEFS']['ROOT_DIR_HW'] + '/' + netlist for netlist in moduleList.getAllDependenciesWithPaths('GIVEN_NGCS') + moduleList.getAllDependenciesWithPaths('GIVEN_EDFS') ]

    # Replace any known black boxes
    blackBoxDeps = []
    blackBoxes = module.getAttribute('BLACK_BOX')
    for vlog in sorted(verilogs):
        if(not blackBoxes is None):
            if(vlog in blackBoxes):
                vlog = blackBoxes[vlog]
                blackBoxDeps.append(vlog)
        relpath = model.rel_if_not_abspath(vlog, str(vivadoCompileDirectory))
        newTclFile.write("read_verilog -quiet " + relpath + "\n")
       
    # grab the system verilogs. 
    for sysv in map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths('GIVEN_SYSTEM_VERILOGS')):
        relpath = model.rel_if_not_abspath(sysv, str(vivadoCompileDirectory))
        newTclFile.write("read_verilog -sv -quiet " + relpath + "\n")
    
    for vhd in sorted(globalVHDs):
        if(isinstance(vhd, model.Source.Source)):            
            # Got a source object, potentially more work to do.
            relpath = model.rel_if_not_abspath(vhd.file, str(vivadoCompileDirectory))
            lib = 'work'
            if('lib' in vhd.attributes):
                newTclFile.write("read_vhdl -lib " + vhd.attributes['lib'] + " " + relpath + "\n")
        else:
            # Just got a string
            relpath = model.rel_if_not_abspath(vhd, str(vivadoCompileDirectory))
            newTclFile.write("read_vhdl -lib work " + relpath + "\n")

    for netlist in givenNetlists:
        relpath = model.rel_if_not_abspath(netlist, str(vivadoCompileDirectory))
        newTclFile.write('read_edif ' + relpath + '\n')

    annotationFiles, annotationDeps = generateSynthesisTcl(moduleList, module, vivadoCompileDirectory)

    part = moduleList.getAWBParam('physical_platform_config', 'FPGA_PART_XILINX')
    
    # the out of context option instructs the tool not to place iobuf
    # and friends on the external ports.
 
    # First, elaborate the rtl design. 

    # Obtain the include directories of any other verilog headers.
    inc_dirs = moduleList.getAllDependencies('VERILOG_INC_DIRS')

    # The user might have provided verilog header files.  Make the visible here. 
    for verilog_h in map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths('GIVEN_VERILOG_HS')):
        relpath = os.path.dirname(model.rel_if_not_abspath(verilog_h, str(vivadoCompileDirectory)))
        if relpath not in inc_dirs:
            inc_dirs.append(relpath)

    # add in the present header files 
    inc_dirs.append(model.rel_if_not_abspath(moduleList.env['DEFS']['ROOT_DIR_HW_INC'], str(vivadoCompileDirectory)))

    # For the top module, we don't use out of context.b
    if(module.getAttribute('TOP_MODULE') is None):
        newTclFile.write("synth_design -rtl -mode out_of_context -top " + module.wrapperName() + " -part " + part + " -include_dirs [list " + " ".join(inc_dirs) + "]\n")
    else:
        newTclFile.write("synth_design -rtl -top " + module.wrapperName() + " -part " + part + " -include_dirs [list " + " ".join(inc_dirs) + "]\n")


    for file in annotationFiles:
        newTclFile.write("add_files " + file + "\n")
        if(module.getAttribute('TOP_MODULE') is None):
            newTclFile.write("set_property USED_IN {synthesis implementation out_of_context} [get_files " + file + "]\n")
        else:
            newTclFile.write("set_property USED_IN {synthesis implementation} [get_files " + file + "]\n")

    if(module.getAttribute('TOP_MODULE') is None):
        clockConversion = ""
        useClockConversion = moduleList.getAWBParamSafe('synthesis_tool', 'VIVADO_ENABLE_CLOCK_CONVERSION')
        print " VIVADO CLOCK CONVERSION: " + str(useClockConversion)
        if(useClockConversion > 0):
            clockConversion = " -gated_clock_conversion auto "
        
        newTclFile.write("synth_design  " + clockConversion + " -mode out_of_context -top " + module.wrapperName() + " -part " + part + " -include_dirs [list " + " ".join(inc_dirs) + "]\n")

        newTclFile.write("set_property HD.PARTITION 1 [current_design]\n")
    else:
        newTclFile.write("synth_design -top " + module.wrapperName() + " -part " + part + " -include_dirs [list " + " ".join(inc_dirs) + "]\n")

    newTclFile.write("all_clocks\n")
    newTclFile.write("report_clocks\n")
    newTclFile.write("report_utilization -file " + module.wrapperName() + ".synth.preopt.util\n")
    

    # We should do opt_design here because it will be faster in
    # parallel.  However, opt_design seems to cause downstream
    # problems and needs more testing. 
   
    newTclFile.write("opt_design -quiet\n")

    newTclFile.write("report_utilization -file " + module.wrapperName() + ".synth.opt.util\n")
    newTclFile.write("write_checkpoint -force " + module.wrapperName() + ".synth.dcp\n")
    newTclFile.write("close_project -quiet\n")
    newTclFile.close()
    return [prjPath] + blackBoxDeps + annotationDeps
    def __init__(self, moduleList):
        altera_apm_name = moduleList.compileDirectory + "/" + moduleList.apmName
        qsf_src_dir = moduleList.env["DEFS"]["ROOT_DIR_HW_MODEL"]

        # If the compilation directory doesn't exist, create it.
        if not os.path.exists(moduleList.compileDirectory):
            os.mkdir(moduleList.compileDirectory)

        rel_qsf_src_dir = model.rel_if_not_abspath(qsf_src_dir, moduleList.compileDirectory)

        # pick up awb parameters.
        paramTclFile = moduleList.topModule.moduleDependency["PARAM_TCL"][0]

        ## QA build expects to build sys_cfg_pkg.svh in the build directory
        if os.path.exists(qsf_src_dir + "/sys_cfg_pkg.svh") and not os.path.exists(
            moduleList.compileDirectory + "/sys_cfg_pkg.svh"
        ):
            os.symlink(rel_qsf_src_dir + "/sys_cfg_pkg.svh", moduleList.compileDirectory + "/sys_cfg_pkg.svh")

        altera_qsf = altera_apm_name + ".tcl"
        altera_qpf = altera_apm_name + ".qpf"

        prjFile = open(altera_qsf, "w")

        prjFile.write("package require ::quartus::project\n")
        prjFile.write("package require ::quartus::flow\n")
        prjFile.write("package require ::quartus::incremental_compilation\n")

        # Check for the existence of a project here, so that we can
        # make use of incremental compilation.
        prjFile.write("set created_project [project_exists " + moduleList.apmName + "]\n")
        prjFile.write("if $created_project {\n")
        prjFile.write("    project_open " + moduleList.apmName + " \n")
        prjFile.write("} else  {\n")
        prjFile.write("    project_new " + moduleList.apmName + "\n")
        prjFile.write("}\n\n")

        ##
        ## Define which version of CCI is in use for SystemVerilog packages
        ## imported from outside LEAP.
        ##
        if moduleList.getAWBParamSafe("qa_platform_libs", "CCI_S_IFC"):
            prjFile.write('set_global_assignment -name VERILOG_MACRO "MPF_PLATFORM_OME=1"\n')
        if moduleList.getAWBParamSafe("qa_platform_libs", "CCI_P_IFC"):
            prjFile.write('set_global_assignment -name VERILOG_MACRO "MPF_PLATFORM_BDX=1"\n')
            prjFile.write('set_global_assignment -name VERILOG_MACRO "BSV_POSITIVE_RESET=1"\n')

        prjFile.write("source " + rel_qsf_src_dir + "/ome2_ivt.qsf\n")
        prjFile.write("source " + rel_qsf_src_dir + "/qsf_env_settings.qsf\n")
        prjFile.write("source " + rel_qsf_src_dir + "/qsf_qph_PAR_files.qsf\n")

        # Include file path
        inc_dirs = ["hw/include"]
        for inc in inc_dirs:
            inc = model.rel_if_not_abspath(inc, moduleList.compileDirectory)
            prjFile.write("set_global_assignment -name SEARCH_PATH " + inc + "\n")

        # Include SDC (Tcl) files. These must be included in a specific order to honor dependencies among them.
        sdcs = (
            map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths("GIVEN_TCL_HEADERS"))
            + map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths("GIVEN_SDCS"))
            + map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths("GIVEN_SDC_ALGEBRAS"))
        )

        for tcl_header in [paramTclFile] + sdcs:
            prjFile.write(
                "set_global_assignment -name SDC_FILE "
                + model.rel_if_not_abspath(tcl_header, moduleList.compileDirectory)
                + "\n"
            )

        # List SystemVerilog packages first
        for pkg in moduleList.getAllDependenciesWithPaths("GIVEN_VERILOG_PKGS"):
            v = model.rel_if_not_abspath(pkg, moduleList.compileDirectory)
            prjFile.write("set_global_assignment -name SYSTEMVERILOG_FILE " + v + "\n")

        # Add in all the verilog here.
        [globalVerilogs, globalVHDs] = synthesis_library.globalRTLs(moduleList, moduleList.moduleList)

        # gather verilog for LI Modules.
        for module in [mod for mod in moduleList.synthBoundaries()] + [moduleList.topModule]:
            globalVerilogs += [model.get_temp_path(moduleList, module) + module.wrapperName() + ".v"]

        for v in globalVerilogs:
            t = "VERILOG"
            if (v[-2:] == "sv") or (v[-2:] == "vh"):
                t = "SYSTEMVERILOG"
            v = model.rel_if_not_abspath(v, moduleList.compileDirectory)
            prjFile.write("set_global_assignment -name " + t + "_FILE " + v + "\n")

        for v in globalVHDs:
            v = model.rel_if_not_abspath(v, moduleList.compileDirectory)
            prjFile.write("set_global_assignment -name VHDL_FILE " + v + "\n")

        # add the verilogs of the files generated by quartus system builder
        for v in model.Utils.clean_split(moduleList.env["DEFS"]["GIVEN_ALTERAVS"], sep=" "):
            v = model.rel_if_not_abspath(v, moduleList.compileDirectory)
            prjFile.write("set_global_assignment -name VERILOG_FILE " + v + "\n")

        fullCompilePath = os.path.abspath(moduleList.compileDirectory)

        # elaborate the design.
        prjFile.write(
            'execute_module  -tool map -args "--verilog_macro=\\"QUARTUS_COMPILATION=1\\" --lib_path '
            + fullCompilePath
            + '--incremental_compilation=full_incremental_compilation --analysis_and_elaboration " \n'
        )

        prjFile.write('puts "Elaboration Complete"\n')
        # create a partition for leap and the QA driver if they don't exist already.
        prjFile.write("if $created_project { \n")
        prjFile.write('    puts "Reusing existing LEAP partitions"\n')
        prjFile.write("} else  { \n")
        prjFile.write(
            "    create_partition -contents cci_std_afu:cci_std_afu|mk_model_Wrapper:model_wrapper|mk_platform_platform_Wrapper:m_sys_sys_vp_m_mod|mkQADeviceSynth:llpi_phys_plat_qa_device -partition qa_cci_part \n"
        )
        prjFile.write("} \n")

        ## Hack to meet timing -- turning off LEAP partition
        partition_mode = moduleList.getAWBParamSafe("qa_device", "CCI_LOOPBACK_HACK")
        if partition_mode < 2:
            prjFile.write('set_partition -partition qa_cci_part -netlist_type "Post-Fit"\n')
        else:
            prjFile.write('set_partition -partition qa_cci_part -netlist_type "Empty"\n')

        #        if (partition_mode < 1):
        #            prjFile.write('set_partition -partition leap_part -netlist_type "Post-Fit"\n')
        #        else:
        #            prjFile.write('set_partition -partition leap_part -netlist_type "Empty"\n')

        prjFile.write(
            'execute_module  -tool map -args "--verilog_macro=\\"QUARTUS_COMPILATION=1\\" --incremental_compilation=full_incremental_compilation --lib_path '
            + fullCompilePath
            + ' " \n'
        )
        prjFile.write('execute_module  -tool cdb -args "--merge"  \n')
        prjFile.write("execute_module  -tool fit \n")
        prjFile.write("execute_module  -tool sta \n")
        prjFile.write('execute_module  -tool sta -args "--do_report_timing"\n')
        prjFile.write("execute_module  -tool asm  \n")

        prjFile.write("project_close \n")
        prjFile.close()

        altera_sof = moduleList.env.Command(
            altera_apm_name + ".sof",
            globalVerilogs + globalVHDs + [altera_apm_name + ".tcl"] + [paramTclFile] + sdcs,
            ["cd " + moduleList.compileDirectory + "; quartus_sh -t " + moduleList.apmName + ".tcl"],
        )

        moduleList.topModule.moduleDependency["BIT"] = [altera_sof]

        # generate the download program
        newDownloadFile = open("config/" + moduleList.apmName + ".download.temp", "w")
        newDownloadFile.write("#!/bin/sh\n")
        newDownloadFile.write("nios2-configure-sof " + altera_apm_name + ".sof\n")
        newDownloadFile.close()

        altera_download = moduleList.env.Command(
            "config/" + moduleList.apmName + ".download",
            "config/" + moduleList.apmName + ".download.temp",
            ["cp $SOURCE $TARGET", "chmod 755 $TARGET"],
        )

        altera_loader = moduleList.env.Command(
            moduleList.apmName + "_hw.errinfo",
            moduleList.swExe + moduleList.topModule.moduleDependency["BIT"] + altera_download,
            [
                "@ln -fs " + moduleList.swExeOrTarget + " " + moduleList.apmName,
                SCons.Script.Delete(moduleList.apmName + "_hw.exe"),
                SCons.Script.Delete(moduleList.apmName + "_hw.vexe"),
                '@echo "++++++++++++ Post-Place & Route ++++++++"',
                synthesis_library.leap_physical_summary(
                    altera_apm_name + ".sta.rpt",
                    moduleList.apmName + "_hw.errinfo",
                    "Timing Analyzer was successful",
                    "Timing requirements not met",
                ),
            ],
        )

        moduleList.topModule.moduleDependency["LOADER"] = [altera_loader]
        moduleList.topDependency = moduleList.topDependency + [altera_loader]
Example #8
0
    edfFile = build_dir + '/' + module.wrapperName() + '.edf'
    resourceFile = build_dir + '/' + module.wrapperName() + '.resources'
    srrFile = build_dir + '/' + module.wrapperName() + '.srr'

    if (not 'GEN_NGCS' in module.moduleDependency):
        module.moduleDependency['GEN_NGCS'] = [edfFile]
    else:
        module.moduleDependency['GEN_NGCS'] += [edfFile]

    [moduleVerilogs,
     moduleVHDs] = synthesis_library.getModuleRTLs(moduleList, module)

    # area group modules have a different base dependency than normal
    # modules
    wrapperVerilogDependency = model.get_temp_path(
        moduleList, module) + module.wrapperName() + '_stub.v'
    if (not module.getAttribute('AREA_GROUP') is None):
        # grab the parent stub?
        wrapperVerilogDependency = model.get_temp_path(
            moduleList, module) + module.wrapperName() + '.v'

    sub_netlist = moduleList.env.Command(
        [edfFile, srrFile],
        [wrapperVerilogDependency] + blackBoxDeps +
        sorted(moduleList.getDependencies(module, 'VERILOG')) +
        moduleVerilogs + moduleVHDs +
        sorted(moduleList.getAllDependencies('VERILOG_LIB')) + sorted(
            model.convertDependencies(
                moduleList.getDependencies(module, 'VERILOG_STUB'))) +
        [newPrjPath] + annotationFiles + annotationDeps +
        ['config/' + moduleList.apmName + '.synplify.prj'],
Example #9
0
    def __init__(self, moduleList):
        altera_apm_name = moduleList.compileDirectory + '/' + moduleList.apmName

        # pick up awb parameters.
        paramTclFile = moduleList.topModule.moduleDependency['PARAM_TCL'][0]

        # If the compilation directory doesn't exist, create it. 
        if(not os.path.exists(moduleList.compileDirectory)):
            os.mkdir(moduleList.compileDirectory)

        newPrjFile = open(altera_apm_name + '.tcl', 'w')

        newPrjFile.write('package require ::quartus::project\n')
        newPrjFile.write('package require ::quartus::flow\n')

        # do we want to check for the existence of a project here?
        newPrjFile.write('project_new ' + moduleList.apmName +' -overwrite\n')

        # Add in all the verilog here. 
        [globalVerilogs, globalVHDs] = synthesis_library.globalRTLs(moduleList, moduleList.moduleList)
         

        # gather verilog for LI Modules. 
        for module in [ mod for mod in moduleList.synthBoundaries()] + [moduleList.topModule]:
            globalVerilogs += [model.get_temp_path(moduleList,module) + module.wrapperName() + '.v']

        # Write files to the quartus project file. Due to a bug in the STA tool, we need to execute 
        # Quartus from the compileDirectory. This means we have to rebase all of the files.

        for v in globalVerilogs:
            newPrjFile.write('set_global_assignment -name VERILOG_FILE ' +  model.rel_if_not_abspath(v, moduleList.compileDirectory) + '\n'); 


        for v in globalVHDs:
            newPrjFile.write('set_global_assignment -name VHDL_FILE ' + model.rel_if_not_abspath(v, moduleList.compileDirectory) + '\n'); 

        for sysVerilogFile in  map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths('GIVEN_SYSTEM_VERILOGS')):
            newPrjFile.write('set_global_assignment -name SYSTEMVERILOG_FILE ' + model.rel_if_not_abspath(sysVerilogFile, moduleList.compileDirectory)+ '\n')

        # Altera flows appear to accept some kinds of memory intialization files. 
        # incorporate them here.
        for memFile in map(model.modify_path_hw,moduleList.getAllDependenciesWithPaths('GIVEN_MIFS') + moduleList.getAllDependenciesWithPaths('GIVEN_MIFS')):
            newPrjFile.write('set_global_assignment -name SOURCE_FILE ' + model.rel_if_not_abspath(memFile, moduleList.compileDirectory)+ '\n')

        print " Compile directory : " + moduleList.compileDirectory

        # add the verilogs of the files generated by quartus system builder
        for v in model.Utils.clean_split(moduleList.env['DEFS']['GIVEN_ALTERAVS'], sep = ' ') :
            newPrjFile.write('set_global_assignment -name VERILOG_FILE ' +  model.rel_if_not_abspath(v, moduleList.compileDirectory) + '\n'); 

        # Include SDC (Tcl) files. These must be included in a specific order to honor dependencies among them.
        sdcs = map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths('GIVEN_TCL_HEADERS')) + map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths('GIVEN_SDCS')) + map(model.modify_path_hw, moduleList.getAllDependenciesWithPaths('GIVEN_SDC_ALGEBRAS'))      

        for tcl_header in [paramTclFile] + sdcs:
            newPrjFile.write('set_global_assignment -name SDC_FILE ' + model.rel_if_not_abspath(tcl_header, moduleList.compileDirectory)+ '\n')

        newPrjFile.write('set_global_assignment -name TOP_LEVEL_ENTITY ' + moduleList.topModule.wrapperName() + '\n')

        for qsf in map(model.modify_path_hw,moduleList.getAllDependenciesWithPaths('GIVEN_QSFS')):
            newPrjFile.write('source ' + model.rel_if_not_abspath(qsf, moduleList.compileDirectory)+ '\n')

        fullCompilePath = os.path.abspath(moduleList.compileDirectory)

        newPrjFile.write('execute_module  -tool map -args "--verilog_macro=\\"QUARTUS_COMPILATION=1\\" --lib_path ' + fullCompilePath + ' " \n')
        newPrjFile.write('execute_module  -tool fit \n')
        newPrjFile.write('execute_module  -tool sta \n')
        newPrjFile.write('execute_module  -tool sta -args "--do_report_timing"\n')
        newPrjFile.write('execute_module  -tool asm  \n')

        newPrjFile.write('project_close \n')
        newPrjFile.close()

        altera_sof = moduleList.env.Command(altera_apm_name + '.sof',
                                            globalVerilogs + globalVHDs + [altera_apm_name + '.tcl'] + [paramTclFile] + sdcs,
                                            ['cd ' + moduleList.compileDirectory + '; quartus_sh -t ' + moduleList.apmName + '.tcl' ])


        moduleList.topModule.moduleDependency['BIT'] = [altera_sof]

        # generate the download program
        newDownloadFile = open('config/' + moduleList.apmName + '.download.temp', 'w')
        newDownloadFile.write('#!/bin/sh\n')
        
        fpgaPosition = moduleList.getAWBParam('physical_platform_config', 'FPGA_POSITION')
        newDownloadFile.write('nios2-configure-sof --device ' + str(fpgaPosition) + ' ' +  altera_apm_name + '.sof\n')
        newDownloadFile.close()

        altera_download = moduleList.env.Command(
            'config/' + moduleList.apmName + '.download',
            'config/' + moduleList.apmName + '.download.temp',
            ['cp $SOURCE $TARGET',
             'chmod 755 $TARGET'])

        altera_loader = moduleList.env.Command(
            moduleList.apmName + '_hw.errinfo',
            moduleList.swExe + moduleList.topModule.moduleDependency['BIT'] + altera_download,
            ['@ln -fs ' + moduleList.swExeOrTarget + ' ' + moduleList.apmName,
             SCons.Script.Delete(moduleList.apmName + '_hw.exe'),
             SCons.Script.Delete(moduleList.apmName + '_hw.vexe'),
             '@echo "++++++++++++ Post-Place & Route ++++++++"',
             synthesis_library.leap_physical_summary(altera_apm_name + '.sta.rpt', moduleList.apmName + '_hw.errinfo', 'Timing Analyzer was successful', 'Timing requirements not met')])

        moduleList.topModule.moduleDependency['LOADER'] = [altera_loader]
        moduleList.topDependency = moduleList.topDependency + [altera_loader]