def logic():
if not aluop[0] and not aluop[1]:
control_out.next = intbv('0010')
elif aluop[0]:
control_out.next = intbv('0110')
elif aluop[1]:
if bin(funct_field[3:], 4) == '0000':
control_out.next = intbv('0010')
elif bin(funct_field[3:], 4) == '0010':
control_out.next = intbv('0110')
elif bin(funct_field[3:], 4) == '0100':
control_out.next = intbv('0000')
elif bin(funct_field[3:], 4) == '0101':
control_out.next = intbv('0001')
elif bin(funct_field[3:], 4) == '1010':
control_out.next = intbv('0111')
else:
control_out.next = intbv(0)
def stimulus():
for op_value in [0, int('100011', 2), int('101011', 2), int('000100', 2)]:
opcode.next = op_value
yield delay(10)
print 'opcode: ', bin(opcode, 6)
print RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, bin(ALUop, 2)
def testRandomLong(self):
for j in range(SIZE):
k = randrange(sys.maxint)
i = k + sys.maxint
self.assertEqual(bin(i), binref(i))
i = -k - sys.maxint
self.assertEqual(bin(i), binref(i))
def testRandomLong(self):
for j in range(SIZE):
k = randrange(sys.maxsize)
i = k + sys.maxsize
assert bin(i) == binref(i)
i = -k - sys.maxsize
assert bin(i) == binref(i)
def logic():
for i in range(1 << bits):
bin_value.next = i
yield delay(1)
print bin(bin_value, bits), bin(gray_value,
bits), bin(bin_value_2, bits)
assert bin_value == bin_value_2
def logic():
if not aluop[0] and not aluop[1]:
control_out.next = intbv('0010')
elif aluop[0]:
control_out.next = intbv('0110')
elif aluop[1]:
if bin(funct_field[3:], 4) == '0000':
control_out.next = intbv('0010')
elif bin(funct_field[3:], 4) == '0010':
control_out.next = intbv('0110')
elif bin(funct_field[3:], 4) == '0100':
control_out.next = intbv('0000')
elif bin(funct_field[3:], 4) == '0101':
control_out.next = intbv('0001')
elif bin(funct_field[3:], 4) == '1010':
control_out.next = intbv('0111')
else:
control_out.next = intbv(0)
def testRandomLong(self):
for j in range(SIZE):
k = randrange(sys.maxsize)
i = k + sys.maxsize
assert bin(i) == binref(i)
i = -k - sys.maxsize
assert bin(i) == binref(i)
def stimulus():
for i in range(8):
value = random.randint(-(2**15), 2**15-1)
data_in.next = intbv( value, min=-(2**15), max=2**15-1)
print "In: %s (%i) | Out: %s (%i)" % (bin(data_in, 16), data_in, bin(data_out, 32), data_out)
yield delay(5)
def testRandomLongWith(self):
for j in range(SIZE):
w = randrange(1, 1000)
k = randrange(sys.maxint)
i = k + sys.maxint
self.assertEqual(bin(i, w), binref(i, w))
i = -k - sys.maxint
self.assertEqual(bin(i, w), binref(i, w))
def testRandomLongWith(self):
for j in range(SIZE):
w = randrange(1, 1000)
k = randrange(sys.maxsize)
i = k + sys.maxsize
assert bin(i, w) == binref(i, w)
i = -k - sys.maxsize
assert bin(i, w) == binref(i, w)
def testRandomLongWith(self):
for j in range(SIZE):
w = randrange(1, 1000)
k = randrange(sys.maxsize)
i = k + sys.maxsize
assert bin(i, w) == binref(i, w)
i = -k - sys.maxsize
assert bin(i, w) == binref(i, w)
def simulate():
print('A B Cin SumOut Cout')
for i in range(10):
A.next, B.next, C_in.next = [randrange(2) for i in range(3)]
yield delay(10)
print('{} {} {} {} {}'.format(bin(A, 1), bin(B, 1),
bin(C_in, 1),
bin(Sum_out, 1),
bin(C_out, 1)))
def stimulus():
for op_value in [
0, int('100011', 2),
int('101011', 2),
int('000100', 2)
]:
opcode.next = op_value
yield delay(10)
print 'opcode: ', bin(opcode, 6)
print RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, bin(
ALUop, 2)
def stimulus():
for i in range(4):
aluop_i.next = intbv(i)
for j in range(2**6):
funct_field_i.next = intbv(j)
yield delay(10)
print("aluop: %s | funct field: %s | alu_control_lines: %s" %
(bin(aluop_i, 2), bin(funct_field_i,
6), bin(alu_control_lines, 4)))
def check_segment_output_proc():
while True:
yield anodos
yield hdl.delay(5) # wait for combinatorial outputs
if anodos == 0b0001:
assert segmentos == get_segment_out(
index_text
), "Error: output mismatch. Index = {0}, anodos = {1}, segment_o = {2}".format(
index_text, anodos, hex(segmentos))
elif anodos == 0b0010:
assert segmentos == get_segment_out(
(index_text + 1) % len(text)
), "Error: output mismatch. Index = {0}, anodos = {1}, segment_o = {2}".format(
index_text, anodos, hex(segmentos))
elif anodos == 0b0100:
assert segmentos == get_segment_out(
(index_text + 2) % len(text)
), "Error: output mismatch. Index = {0}, anodos = {1}, segment_o = {2}".format(
index_text, anodos, hex(segmentos))
elif anodos == 0b1000:
assert segmentos == get_segment_out(
(index_text + 3) % len(text)
), "Error: output mismatch. Index = {0}, anodos = {1}, segment_o = {2}".format(
index_text, anodos, hex(segmentos))
else:
yield hdl.Error("Invalid patter for anodos: {}".format(
hdl.bin(anodos, width=4)))
def stimulus():
iA, iB, pA, pB = 0, 0, 1, 1
yield clk.negedge
rst.next = False
while True:
yield clk.negedge
a.next = randrange(-MAX, MAX)
b.next = randrange(-MAX, MAX)
pipeA[iA].next = a
pipeB[iB].next = b
iA = (iA + 1) % ticks
iB = (iB + 1) % ticks
if (p != pipeA[pA] * pipeB[pB]):
f_a = float(a)
f_b = float(b)
f_p = float(p)
f_pipeA = float(pipeA[pA])
f_pipeB = float(pipeB[pB])
print("{:5.4f}x{:5.4f} = {:5.4f}".format(
f_a / float(MAX), f_b /
float(MAX), (f_pipeA * f_pipeB) / float(MAXOUT)) +
" but got {:5.4f}, error: {:5.4f}".format(
f_p / float(MAXOUT), (f_pipeA * f_pipeB - f_p) /
float(MAXOUT)))
assert p == pipeA[iA] * pipeB[iB], \
"Difference: p - a * b = {}".format(
bin(p - pipeA[iA] * pipeB[pB], 2 * BITS))
pA = (pA + 1) % ticks
pB = (pB + 1) % ticks
def stimulus():
iA, iB, pA, pB = 0, 0, 1, 1
yield clk.negedge
rst.next = False
while True:
yield clk.negedge
a.next = randrange(-MAX, MAX)
b.next = randrange(-MAX, MAX)
pipeA[iA].next = a
pipeB[iB].next = b
iA = (iA + 1) % ticks
iB = (iB + 1) % ticks
if (p != pipeA[pA] * pipeB[pB]):
f_a = float(a)
f_b = float(b)
f_p = float(p)
f_pipeA = float(pipeA[pA])
f_pipeB = float(pipeB[pB])
print("{:5.4f}x{:5.4f} = {:5.4f}".format(
f_a/float(MAX), f_b/float(MAX),
(f_pipeA * f_pipeB)/float(MAXOUT)) +
" but got {:5.4f}, error: {:5.4f}".format(
f_p/float(MAXOUT),
(f_pipeA * f_pipeB - f_p)/float(MAXOUT)))
assert p == pipeA[iA] * pipeB[iB], \
"Difference: p - a * b = {}".format(
bin(p - pipeA[iA] * pipeB[pB], 2 * BITS))
pA = (pA + 1) % ticks
pB = (pB + 1) % ticks
def stimulus():
for control_val, func in [(int(b, 2), func) for (b, func) in control_func]:
control_i.next = Signal(intbv(control_val))
op1_i.next, op2_i.next = [intbv(random.randint(0, 255))[32:] for i in range(2)]
yield delay(10)
print "Control: %s | %i %s %i | %i | z=%i" % (bin(control_i, 4), op1_i, func, op2_i, out_i, zero_i)
def test(B, G, width):
B.next = intbv(0)
yield delay(10)
for i in range(1, 2**width):
G_Z.next = G
B.next = intbv(i)
yield delay(10)
diffcode = bin(G ^ G_Z)
self.assertEqual(diffcode.count('1'), 1)
def test(B, G, G_Z, width):
B.next = intbv(0)
yield delay(10)
for i in range(1, 2**width):
G_Z.next = G
B.next = intbv(i)
yield delay(10)
diffcode = bin(G ^ G_Z)
self.assertEqual(diffcode.count('1'), 1)
def stimulus():
for step in range(STEPS):
print "STEP %02d:" % step,
a.next = step
b.next = step << 8
if step % 2 == 0:
sel.next = not sel
yield DELAY
print "%d q %s a %s b %s" % (sel, bin(q, 16), bin(a, 16), bin(b, 16))
if sel % 2 == 0:
assert q == a
else:
assert q == b
raise StopSimulation
def debug_internals():
sep = "\n" + "=" * 31 + " cycle %i (%ins)" + "=" * 31
print sep % (int(now() / 2.0 + 0.5), now())
#IF
print "\n" + "." * 35 + " IF " + "." * 35 + "\n"
print "PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %x" % (PcAdderOut_if, BranchAdderO_mem, PCSrc_mem, NextIp, Ip)
print 'Instruction_if %s (%x)' % (bin(Instruction_if, 32), Instruction_if)
if True: # now () > 2:
#ID
print "\n" + "." * 35 + " ID " + "." * 35 + "\n"
print "Ip_id %i | Instruction_id %s (%x) | Nop %i" % (PcAdderOut_id, bin(Instruction_id, 32), Instruction_id, NopSignal)
print 'Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i' % \
(bin(Opcode_id, 6), Rs_id, Rt_id, Rd_id, Func_id, Address16_id, Address32_id)
print 'Data1 %i | Data2 %i' % (Data1_id, Data2_id)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i Jump %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
(RegDst_id, ALUop_id, ALUSrc_id, Branch_id, Jump_id, MemRead_id, MemWrite_id, RegWrite_id, MemtoReg_id)
print 'Stall --> %i' % Stall
if True: # if now () > 4:
#EX
print "\n" + "." * 35 + " EX " + "." * 35 + "\n"
print "Ip_ex %i | BranchAdderO_ex %i " % (PcAdderOut_ex, BranchAdderO_ex)
print "Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" % (Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex)
print 'Data1_ex %i | Data2_ex %i' % (Data1_ex, Data2_ex)
print 'ForwardA %i | ForwardB %i' % (ForwardA, ForwardB)
print 'ForwMux1Out %i | ForwMux2Out %i' % (ForwMux1Out, ForwMux2Out)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i Jump %i, MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
(RegDst_ex, ALUop_ex, ALUSrc_ex, Branch_ex, Jump_ex, MemRead_ex, MemWrite_ex, RegWrite_ex, MemtoReg_ex)
print '--> ALU'
print 'MuxAluDataSrc %i | AluCtrl %s | AluResult_ex %i | Zero_ex %i' % (MuxAluDataSrc_ex, AluControl, AluResult_ex, Zero_ex)
print 'WrRegDest_ex %i' % WrRegDest_ex
def stimulus():
for i in range(4):
aluop_i.next = intbv(i)
for j in range(2**6):
funct_field_i.next = intbv(j)
yield delay(10)
print "aluop: %s | funct field: %s | alu_control_lines: %s" % (bin(aluop_i, 2), bin(funct_field_i, 6 ), bin(alu_control_lines, 4))
def get_arg(instruction, argument):
"""
Utiity function to return commonly used slices/arguments
of instructions in hexadecimal or binary formats
:param Signal instruction: Input instruction
:param str argument_name: the name of the argument to be extracted
"""
if argument == 'family_code':
return instruction[7:2]
elif argument == 'opcode':
return instruction[7:]
elif argument == 'funct3':
return instruction[15:12]
elif argument == 'funct7':
return instruction[32:25]
elif argument == 'rs1':
return instruction[20:15]
elif argument == 'rs2':
return instruction[25:20]
elif argument == 'imm12lo':
return intbv(int(bin(instruction[31]) + bin(instruction[7]) + bin(instruction[31:27], width=4),2))
elif argument == 'imm12hi':
return intbv(int(bin(instruction[27:25],width=2) + bin(instruction[12:8],width=4) ,2))
elif argument == 'instruction_id':
return instruction[15:12]
elif argument == 'rd':
return instruction[12:7]
elif argument == 'imm12':
return instruction[32:20]
elif argument == 'imm12_sb':
return intbv(int(bin(instruction[32:25],width=7) + bin(instruction[12:7],width=5) ,2))
elif argument == 'imm20':
return intbv(int( bin(instruction[31]) + bin(instruction[20:12],width=8) + bin(instruction[20]) + bin(instruction[31:21], width=10) ,2))
elif argument == 'imm20_pc':
return instruction[31:12]
elif argument == 'shamtw':
return instruction[25:20]
elif argument == 'shamt':
return instruction[25:20]
else:
return None
def test(B, G):
w = len(B)
G_Z = Signal(intbv(0)[w:])
B.next = intbv(0)
yield delay(10)
for i in range(1, 2**w):
G_Z.next = G
B.next = intbv(i)
yield delay(10)
diffcode = bin(G ^ G_Z)
self.assertEqual(diffcode.count('1'), 1)
def stimulus():
print("{:>8}\t{:>8}\t{}".format("X", "Y", "OUT"))
for x_next, y_next in product(range(8), range(8)):
X.next = intbv(x_next)
Y.next = intbv(y_next)
yield delay(10)
print(
"{:>8}".format(ENCODING[int(X)]),
"{:>8}".format(ENCODING[int(Y)]),
"{:>3}".format(bin(OUT, 2)),
sep="\t")
def test(B, G):
w = len(B)
G_Z = Signal(intbv(0)[w:])
B.next = intbv(0)
yield delay(10)
for i in range(1, 2**w):
G_Z.next = G
B.next = intbv(i)
yield delay(10)
diffcode = bin(G ^ G_Z)
self.assertEqual(diffcode.count('1'), 1)
def stimulus():
for control_val, func in [(int(b, 2), func)
for (b, func) in control_func]:
control_i.next = Signal(intbv(control_val))
op1_i.next, op2_i.next = [
intbv(random.randint(0, 255))[32:] for i in range(2)
]
yield delay(10)
print "Control: %s | %i %s %i | %i | z=%i" % (bin(
control_i, 4), op1_i, func, op2_i, out_i, zero_i)
def debug_internals():
print "-" * 78
print "time %s | clk %i | clk_pc %i | ip %i " % (now(), clk,
clk_pc, ip)
print 'pc_add_o %i | branch_add_o %i | BranchZ %i | next_ip %i' % (
pc_adder_out, branch_adder_out, branchZ, next_ip)
print 'instruction', bin(instruction, 32)
print 'opcode %s | rs %i | rt %i | rd %i | shamt %i | func %i | address %i' % \
(bin(opcode, 6), rs, rt, rd, shamt, func, address)
print 'wr_reg_in %i | dat1 %i | dat2 %i | muxALUo %i ' % \
(wr_reg_in, data1, data2, mux_alu_out)
print 'RegDst %i | ALUSrc %i | Mem2Reg %i | RegW %i | MemR %i | MemW %i | Branch %i | ALUop %s' % (
RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch,
bin(ALUop, 2))
print 'func: %s | aluop: %s | alu_c_out: %s' % (bin(
func, 5), bin(ALUop, 2), bin(alu_control_out, 4))
print 'ALU_out: %i | Zero: %i' % (alu_out, zero)
print 'ram_out %i | mux_ram_out %i ' % (ram_out, mux_ram_out)
def debug_internals():
print "-" * 78
print "time %s | clk %i | clk_pc %i | ip %i " % (now(), clk, clk_pc, ip)
print 'pc_add_o %i | branch_add_o %i | BranchZ %i | next_ip %i' % (pc_adder_out, branch_adder_out, branchZ, next_ip)
print 'instruction', bin(instruction, 32)
print 'opcode %s | rs %i | rt %i | rd %i | shamt %i | func %i | address %i' % \
(bin(opcode, 6), rs, rt, rd, shamt, func, address)
print 'wr_reg_in %i | dat1 %i | dat2 %i | muxALUo %i ' % \
(wr_reg_in, data1, data2, mux_alu_out)
print 'RegDst %i | ALUSrc %i | Mem2Reg %i | RegW %i | MemR %i | MemW %i | Branch %i | ALUop %s' % (RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, bin(ALUop, 2))
print 'func: %s | aluop: %s | alu_c_out: %s' % (bin(func, 5),
bin(ALUop, 2),
bin(alu_control_out, 4))
print 'ALU_out: %i | Zero: %i' % (alu_out, zero)
print 'ram_out %i | mux_ram_out %i ' % (ram_out, mux_ram_out)
def run():
# the coming steps done to load the register file with values
REGwrite.next = 1 # enable writing into the register file
rd.next = 0b010 # giving the address the data to be stored
data.next = 0b011 # assigning the value of the data
yield (clock.negedge) # wait for the negative edge
print(
'Assign x', rd, ' = ', int(data), sep=''
) # print which address the data will be store and the value of the data
rd.next = 0b011 # giving the address the data to be stored
data.next = 0b101 # assigning the value of the data
yield (clock.negedge) # wait for the negative edge
print(
'Assign x', rd, ' = ', int(data), sep=''
) # print which address the data will be store and the value of the data
rd.next = 0b100 # giving the address the data to be stored
data.next = 0b101101010101 # assigning the value of the data
yield (clock.negedge) # wait for the negative edge
print(
'Assign x', rd, ' = ', int(data), sep=''
) # print which address the data will be store and the value of the data
REGwrite.next = 0 # done loading the register file
rs1IN.next = 0b010 # take the register number 2 (x2) as an input
rs2IN.next = 0b011 # take the register number 3 (x3) as an input
yield clock.negedge # wait for the negative edge
print('rs1IN=x', rs1IN, ' rs2IN=x', rs2IN,
sep='') # printing the input registers addresses
print('rs1OUT=', int(bin(rs1out), 2), 'rs2OUT=',
int(bin(rs2out),
2)) # printing the value stored in the input addresses
print()
def _vcd_printval(self, value):
if isinstance(value, myhdl.SignalType):
thevalue = value.val
if value._nrbits == 1:
return str(int(thevalue))
else:
thevalue = value
if isinstance(thevalue, myhdl.intbv):
if thevalue._nrbits == 1:
return str(int(thevalue))
else:
return "b%s " % myhdl.bin(thevalue)
elif isinstance(thevalue, bool):
return str(int(thevalue))
elif isinstance(thevalue, (int, long)):
return "b%s " % myhdl.bin(thevalue)
elif isinstance(thevalue, float):
return "r%.16g " % thevalue
elif isinstance(thevalue, str):
return "s%s " % thevalue
else:
# use repr as fallback
return "s%s " % repr(thevalue)
def _vcd_printval(self, value):
if isinstance(value, myhdl.SignalType):
thevalue = value.val
if value._nrbits == 1:
return str(int(thevalue))
else:
thevalue = value
if isinstance(thevalue, myhdl.intbv):
if thevalue._nrbits == 1:
return str(int(thevalue))
else:
return "b%s " % myhdl.bin(thevalue)
elif isinstance(thevalue, bool):
return str(int(thevalue))
elif isinstance(thevalue, (int, long)):
return "b%s " % myhdl.bin(thevalue)
elif isinstance(thevalue, float):
return "r%.16g " % thevalue
elif isinstance(thevalue, str):
return "s%s " % thevalue
else:
# use repr as fallback
return "s%s " % repr(thevalue)
def transmit(char):
yield baud_ticks(self.UART_RX_BAUD_DIV)
self.rx.next = self.LVL_START
yield baud_ticks(self.UART_RX_BAUD_DIV)
indexes = range(8)[::-1]
for i in indexes:
lvl = bin(char, width=8)[i] == '1'
self.rx.next = lvl
yield baud_ticks(self.UART_RX_BAUD_DIV)
self.rx.next = self.LVL_STOP
yield baud_ticks(self.UART_RX_BAUD_DIV)
def run():
address.next = 1
INdata.next = 0b00000000000000000000010110010011
MEMwrite.next = 1
MEMcontrol.next = 6
MEMread.next = 0
yield delay(10)
print(address, INdata, MEMwrite)
MEMread.next = 1
MEMcontrol.next = 2
address.next = 1
MEMwrite.next = 0
yield delay(10)
print(address, INdata, MEMwrite)
print('out -->', bin(OUTdata, 32))
def stimulus():
print(" A B Control Output")
A.next, B.next, Control.next = -10, 50, 0 # Testing ADD
yield delay(10)
print("the opretion is add: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A), int(B), int(Control), int(Output), int(Zero)))
A.next, B.next, Control.next = -10, 50, 1 # Testing SUB
yield delay(10)
print("the opretion is sub: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A), int(B), int(Control), int(Output), int(Zero)))
A.next, B.next, Control.next = -10, 3, 7 # Testing SLL
yield delay(10)
print("the opretion is SLL: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A), int(B), int(Control), int(Output), int(Zero)))
A.next, B.next, Control.next = -500, 3, 23 # Testing BGEU
yield delay(10)
print("the opretion is BGEU: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A), int(B), int(Control), int(Output), int(Zero)))
A.next, B.next, Control.next = 3, 3, 19 # Testing BNQ
yield delay(10)
print("the opretion is BNQ: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A), int(B), int(Control), int(Output), int(Zero)))
A.next, B.next, Control.next = 0, 10, 24 # Testing LUI
yield delay(10)
print("the opretion is LUI: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A), int(B), int(Control), int(Output), int(Zero)))
A.next, B.next, Control.next = -20, 10, 9 # Testing DIV
yield delay(10)
print("the opretion is DIV: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A), int(B), int(Control), int(Output), int(Zero)))
A.next, B.next, Control.next = -int(429496 / 2), 10, 11 # Testing DIVU
yield delay(10)
print(bin(A.unsigned()))
print(
"the opretion is DIVU: A= %s B= %s Control= %s Ans=%s Zero=%s" %
(int(A.unsigned()), int(B), int(Control), int(Output), int(Zero)))
def test_check_crc():
x = myhdl.intbv(0, _nrbits=22 * 8)
x[:] = 0xAAAAAAAAAAAAAAAAAAABCDEFAAAAAAAAAAAAAAAAAAAA # 13548
crc_poly = myhdl.intbv(0, _nrbits=9)
crc_poly[8] = 1
crc_poly[4] = 1
crc_poly[3] = 1
crc_poly[2] = 1
crc_poly[0] = 1
print(myhdl.bin(x, x._nrbits))
print(myhdl.bin(crc_poly, crc_poly._nrbits))
c, err = check_crc(x, crc_poly)
print(myhdl.bin(c, c._nrbits))
print(myhdl.bin(err, err._nrbits))
d, derr = check_crc(x, crc_poly, err)
print(myhdl.bin(d, d._nrbits))
print(myhdl.bin(derr, derr._nrbits))
def convert_value(data, custom_type=None, type_array=[None, None]):
"""
This function converts data to a string valid in VHDL syntax.
"""
retval = ""
numbits = 0
usedata = data
if custom_type is not None:
# custom type
if custom_type == int:
usedata = int(data)
elif custom_type == bool:
usedata = data == True
elif custom_type == intbv:
# need fixed boundaries. Use type_array
if type_array == [None, None]:
# default: one bit width
usedata = intbv(data)[1:]
else:
# intbv boundaries refer to bit width
usedata = intbv(data)[type_array[1]+1:type_array[0]]
elif custom_type == str:
usedata = str(data)
elif isinstance(custom_type, str):
# type in a string format
if custom_type == "integer":
usedata = int(data)
elif custom_type == "std_logic":
usedata = intbv(data)[1:]
elif custom_type == "string":
usedata = str(data)
elif custom_type.find("std_logic_vector") == 0:
# strip values
vecinfo = custom_type.replace("std_logic_vector", "").strip("()").split()
if vecinfo[1] == "to":
vecmin = int(vecinfo[0])
vecmax = int(vecinfo[2])
elif vecinfo[1] == "downto":
vecmin = int(vecinfo[2])
vecmax = int(vecinfo[0])
usedata = intbv(data)[vecmax+1:vecmin]
else:
raise TypeError("Unsupported custom type string '%s' for VHDL conversion." % custom_type)
else:
raise TypeError("Unsupported custom type '%s' for VHDL conversion." % type(custom_type))
# convert
if isinstance(usedata, int):
retval = "%d" % data
elif isinstance(usedata, bool):
retval = "'%d'" % int(data)
elif isinstance(usedata, intbv):
# check boundaries
if usedata._nrbits > 1:
# print vector in bits
retval = '"%s"' % bin(usedata, usedata._nrbits)
else:
retval = "'%d'" % usedata
elif isinstance(usedata, str):
retval = '"%s"' % usedata
else:
raise TypeError("Unsupported type '%s' for VHDL conversion." % type(usedata))
return retval
def debug_internals():
sep = "\n" + "=" * 34 + " time %s " + "=" * 34
print sep % now()
# IF
print "\n" + "." * 35 + " IF " + "." * 35 + "\n"
print "PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %i" % (
PcAdderOut_if,
BranchAdderO_mem,
PCSrc_mem,
NextIp,
Ip,
)
print "Instruction_if %s (%i)" % (bin(Instruction_if, 32), Instruction_if)
if True: # now () > 2:
# ID
print "\n" + "." * 35 + " ID " + "." * 35 + "\n"
print "PcAdderO_id %i | Instruction_id %s (%i) | Nop %i" % (
PcAdderOut_id,
bin(Instruction_id, 32),
Instruction_id,
NopSignal,
)
print "Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i" % (
bin(Opcode_id, 6),
Rs_id,
Rt_id,
Rd_id,
Func_id,
Address16_id,
Address32_id,
)
print "Data1 %i | Data2 %i" % (Data1_id, Data2_id)
print "-->CONTROL"
print "RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i " % (
RegDst_id,
bin(ALUop_id, 2),
ALUSrc_id,
Branch_id,
MemRead_id,
MemWrite_id,
RegWrite_id,
MemtoReg_id,
)
if True: # if now () > 4:
# EX
print "\n" + "." * 35 + " EX " + "." * 35 + "\n"
print "PcAdderO_ex %i | BranchAdderO_ex %i " % (PcAdderOut_ex, BranchAdderO_ex)
print "Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" % (Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex)
print "Data1_ex %i | Data2_ex %i" % (Data1_ex, Data2_ex)
print "-->CONTROL"
print "RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i " % (
RegDst_ex,
bin(ALUop_ex, 2),
ALUSrc_ex,
Branch_ex,
MemRead_ex,
MemWrite_ex,
RegWrite_ex,
MemtoReg_ex,
)
print "--> ALU"
print "MuxAluDataSrc %i | AluCtrl %s | AluResult_ex %i | Zero_ex %i" % (
MuxAluDataSrc_ex,
bin(AluControl, 4),
AluResult_ex,
Zero_ex,
)
print "WrRegDest_ex %i" % WrRegDest_ex
if True: # if now () > 6:
# MEM
print "\n" + "." * 35 + "MEM " + "." * 35 + "\n"
print "BranchAdderO_mem %i " % (BranchAdderO_mem)
print "-->CONTROL"
print "Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i " % (
Branch_mem,
MemRead_mem,
MemWrite_mem,
RegWrite_mem,
MemtoReg_mem,
)
print "--> Branch"
print "Branch_mem %i Zero %i | PCSrc_mem %i" % (Branch_mem, Zero_mem, PCSrc_mem)
print "--> Data mem"
print "AluResult_mem %i | Data2_mem %i | DataMemOut_mem %i | MemW %i MemR %i" % (
AluResult_mem,
Data2_mem,
DataMemOut_mem,
MemWrite_mem,
MemRead_mem,
)
print "WrRegDest_mem %i" % WrRegDest_mem
if True: # if now() > 8:
# WB
print "\n" + "." * 35 + "WB" + "." * 35 + "\n"
print "CONTROL --> RegW %i Mem2Reg %i " % (RegWrite_mem, MemtoReg_mem)
print "DataMemOut_wb %i | AluResult_wb %i | MuxMemO_wb %i " % (DataMemOut_wb, AluResult_wb, MuxMemO_wb)
print "WrRegDest_wb %i | MuxMemO_wb %i" % (WrRegDest_wb, MuxMemO_wb)
bbbbbb defines the word size in bits (0-32). The default (0) sets 8 bits per word. Auxiliary SPI device only. ''' import pigpio from myhdl import bin,intbv pi1 = pigpio.pi() print pi1 flgs = intbv(0)[22:] flgs = 0 ''' when ch is 0 the cs0 is enabled bcm8 Standard SPI when ch is 1 the cs1 is enabled bcm7 Standard SPI when ch is 0 & flgs is 256 the cs0 is enabled bcm18 Aux SPI flgs 0, 1, 2, or 3 no difference ''' ch = 0 clk_freq = 1000000 print "ch",ch,"flgs",bin(flgs) h = pi1.spi_open(ch,clk_freq,flgs) print "handle",h pi1.spi_write(h, b'\x02\xc0\x80\x01\x02\x03') #pi1.spi_write(h,"abc") (b, d) = pi1.spi_read(h,6) print b, d[0], d[1],d[2],d[3], d[4],d[5] pi1.spi_close(h)
def simulate():
ham = {}
hamSum = 0
bitW = 0
bitC = 0
for p in range(512):
keyset = format(p, "09b")
beforeS = []
beforeS1 = []
beforeS2 = []
beforeC = []
before = []
#print('A B Cin SumOut Cout')
for i in range(128):
K1.next = 0
K2.next = 0
K3.next = 0
K4.next = 0
K5.next = 0
K6.next = 0
K7.next = 0
K8.next = 0
K9.next = 0
set = format(i, "07b")
A.next = int(set[0])
B.next = int(set[1])
C_in.next = int(set[2])
A1.next = int(set[3])
B1.next = int(set[4])
A2.next = int(set[5])
B2.next = int(set[6])
yield delay(10)
#print ('{} {} {} {} {} BEFORE'.format(bin(A,1),bin(B,1),bin(C_in,1),bin(Sum_out,1),bin(C_out,1)))
beforeS.append(int(bin(Sum_out)))
beforeS1.append(int(bin(Sum1_out)))
beforeS2.append(int(bin(Sum2_out)))
beforeC.append(int(bin(C_out)))
before = beforeS + beforeS1 + beforeS2 + beforeC
print('Before:')
print(beforeC)
print(before)
K1.next = int(keyset[0])
K2.next = int(keyset[1])
K3.next = int(keyset[2])
K4.next = int(keyset[3])
K5.next = int(keyset[4])
K6.next = int(keyset[5])
K7.next = int(keyset[6])
K8.next = int(keyset[7])
K9.next = int(keyset[8])
afterS = []
afterS1 = []
afterC = []
afterS2 = []
after = []
for i in range(128):
set = format(i, "07b")
A.next = int(set[0])
B.next = int(set[1])
C_in.next = int(set[2])
A1.next = int(set[3])
B1.next = int(set[4])
A2.next = int(set[5])
B2.next = int(set[6])
yield delay(10)
afterS.append(int(bin(Sum_out)))
afterS1.append(int(bin(Sum1_out)))
afterS2.append(int(bin(Sum2_out)))
afterC.append(int(bin(C_out)))
after = afterS + afterS1 + afterS2 + afterC
print('After:')
print(afterC)
print(after)
t = []
for i in range(len(before)):
bitC += 1
if before[i] != after[i]:
bitW += 1
t.append(before[i])
hamming = len(t) / len(before)
for index, key in enumerate(keyset):
print('Key{}: {}'.format(index, key))
print('Hamming = {}'.format(hamming))
ham[hamming] = p
hamSum += hamming
print('Hamming List:')
print(ham)
smallest = nsmallest(1, ham, key=lambda x: abs(x - 0.5))
key = format(ham[smallest[0]], "09b")
print('Best Key Combination: {}'.format(key))
print('Hamming Distance: {}'.format(smallest))
print('Ave Hamming = {}'.format(hamSum / 511))
print('Wrong {} / {}'.format(bitW, bitC))
print('Percent: {}'.format(bitW / bitC))
def testRandomInt(self):
for j in range(SIZE):
i = randrange(-sys.maxsize, sys.maxsize)
assert bin(i) == binref(i)
def testRandomIntWidth(self):
for j in range(SIZE):
w = randrange(1, 1000)
i = randrange(-sys.maxsize, sys.maxsize)
assert bin(i, w) == binref(i, w)
def test_basic():
# Test all exact single bit values for W(16,0,15)
for f in range(1,16):
x = fixbv(2**-f, format=W(16,0,15))
y = fixbv(-2**-f, format=W(16,0,15))
print(f,x,y)
assert float(x) == 2**-f, \
"%s != %s, %04x != %04x" % (2.**-f, x,
hex(x),
hex(0x8000 >> f))
assert bin(x,16) == bin(0x8000 >> f, 16), \
"%s != %s for f == %d" % (bin(x, 16),
bin(0x8000 >> f, 16), f)
assert float(y) == -2**-f
assert bin(y,16) == bin(-0x8000 >> f, 16), \
"%s" % (bin(y, 16))
# Test all exact single bit values for W128.0
for f in range(1,128):
x = fixbv(2**-f, min=-1, max=1, res=2**-127)
y = fixbv(-2**-f, min=-1, max=1, res=2**-127)
assert float(x) == 2**-f
assert bin(x,128) == bin(0x80000000000000000000000000000000 >> f, 128)
assert float(y) == -2**-f
assert bin(y,128) == bin(-0x80000000000000000000000000000000 >> f, 128)
assert x > y
assert y < x
assert min(x,y) == min(y,x) == y
assert max(x,y) == max(y,x) == x
assert x != y
x = fixbv(3.14159, format=W(18,3))
y = fixbv(-1.4142 - 1.161802 - 2.71828, format=W(18,3))
assert x != y
#assert --x == x
assert abs(y) > abs(x)
assert abs(x) < abs(y)
assert x == x and y == y
# Create a W8.3 fixed-point object value == 2.5
x = fixbv(2.5, min=-8, max=8, res=1./32)
assert float(x) == 2.5
assert int(x) == 0x50
def testSmallWidth(self):
for i in range(-65, 65):
w = randrange(1, 8)
assert bin(i, w) == binref(i, w)
def test_create():
"""
This test creates a bunch of different fixed-point objects.
This test doesn't test correctness only test that creating and many
of the public functions execute without error.
"""
print("\n** Create W16.0 fxintbv")
x = fixbv(0, min=-1, max=1, res=2**-15)
print(x, hex(x), repr(x))
print "\n** Create W9.3 fxintbv == 2.5"
x = fixbv(2.5, min=-8, max=8, res=1./32)
print(x, hex(x), repr(x))
print("\n** Create W0.?? fxintbv == 0.0333")
x = fixbv(0.0333, min=-1, max=1, res=0.0001)
print(x, hex(x), repr(x))
s = 0.5
x = 0x4000
for i in range(16):
fxp = fixbv(s, min=-1, max=1, res=2**-15)
s = s / 2
print(str(fxp), myhdl.bin(fxp, 16), "%04x" % (fxp), type(fxp), repr(fxp))
#print(hex(fxp & x) @todo assert hex(fxp & x) == x, "Incorrect fixed-point calculation")
x = x >> 1
print("Get fixbv")
a = fixbv(0, min=-2, max=2, res=2**-4)
print("Assign to 1")
a._val = 1
print(a, repr(a))
print("[1] Showing range: ")
print("printing a:", a)
print("slice operation (Note slice will return intbv)")
print(" ", str(a), " slice a[4:] ", hex(a[4:]), " a[16:] ", hex(a[16:]))
a = fixbv(1.2, min=-2, max=2, res=2**-3)
print("[2] Showing range: ")
print("printing a: ", a)
a = fixbv(0.02, min=-1, max=1, res=2**-8)
print("[1] Representation a: ", repr(a))
b = fixbv(0.2, min=-1, max=1, res=2**-8)
print("[2] Representation b: ", repr(b))
c = fixbv(0, format=a.W+b.W)
print("[3] Representation c: ", c.W)
print("[1] Add: c = a + b")
c[:] = a + b
print "c: ", c, type(c), repr(c)
print("[2] Add: c = 1.25 + 2.0")
a = fixbv(1.25, min=-4, max=4, res=2**-12)
b = fixbv(2.0, min=-4, max=4, res=2**-12)
c = fixbv(0, format=a.W+b.W)
print(" a: ", a.W, bin(a,len(a)), " b: ", b.W, bin(b,len(b)))
c[:] = a + b
print("c: ", c, c.W, bin(c,len(c)))
def simulus():
for i in range(10):
A.next = randrange(2)
B.next = randrange(2)
yield delay(10)
print "A: " + bin(A,1) + "B: " + bin(B,1) + "|S: " + bin(S,1) + "C: " + bin(C,1)
def decoder_output():
instruction_family = bin(get_arg(instruction, 'family_code'),width=5)
opcode.next = get_arg(instruction, 'opcode')
# Branch Instructions
if instruction_family == '11000':
funct3.next = get_arg(instruction, 'funct3')
funct7.next = intbv(0)
rs1.next = get_arg(instruction, 'rs1')
rs2.next = get_arg(instruction, 'rs2')
imm12lo.next = get_arg(instruction, 'imm12lo')
imm12hi.next = get_arg(instruction, 'imm12hi')
imm12.next = intbv(0)
imm20.next = intbv(0)
shamt.next = intbv(0)
shamtw.next = intbv(0)
rd.next = intbv(0)
rm.next = intbv(0)
arg_list = ['rs1', 'rs2', 'imm12lo', 'imm12hi']
arg_select.next = get_arg_select(arg_list)
# Jump Instructions
elif instruction_family == '11001':
funct3.next = intbv(0)
funct7.next = intbv(0)
rs1.next = get_arg(instruction, 'rs1')
rd.next = get_arg(instruction,'rd')
imm12.next = get_arg(instruction,'imm12')
rs2.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = intbv(0)
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
arg_list = ['rs1', 'rd', 'imm12']
arg_select.next = get_arg_select(arg_list)
elif instruction_family == '11011':
funct3.next = intbv(0)
funct7.next = intbv(0)
rs1.next = intbv(0)
rd.next = get_arg(instruction,'rd')
imm12.next =intbv(0)
rs2.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = get_arg(instruction,'imm20')
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
arg_list = ['rd', 'imm20']
arg_select.next = get_arg_select(arg_list)
# LUI and AUIPC
elif instruction_family == '01101' or instruction_family == '00101':
funct3.next = intbv(0)
funct7.next = intbv(0)
rs1.next = intbv(0)
rd.next = get_arg(instruction,'rd')
imm12.next =intbv(0)
rs2.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = get_arg(instruction,'imm20_pc')
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
arg_list = ['rd', 'imm20']
arg_select.next = get_arg_select(arg_list)
# Addition and Logical immediate Instructions
elif instruction_family == '00100':
funct3.next = get_arg(instruction, 'funct3')
rs1.next = get_arg(instruction,'rs1')
rd.next = get_arg(instruction,'rd')
imm12.next = intbv(0)
rs2.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
if get_arg(instruction, 'funct3') in [1,5]:
shamt.next = get_arg(instruction,'shamt')
funct7.next = get_arg(instruction, 'funct7')
imm12.next = intbv(0)
arg_list = ['rs1', 'rd', 'shamt']
arg_select.next = get_arg_select(arg_list)
else :
shamt.next = intbv(0)
funct7.next = intbv(0)
imm12.next = get_arg(instruction,'imm12')
arg_list = ['rs1', 'rd', 'imm12']
arg_select.next = get_arg_select(arg_list)
# Addition and Logical Instructions
elif instruction_family == '01100':
funct3.next = get_arg(instruction,'funct3')
funct7.next = intbv(0)
rs1.next = get_arg(instruction,'rs1')
rs2.next = get_arg(instruction,'rs2')
rd.next = get_arg(instruction,'rd')
imm12.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = intbv(0)
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
arg_list = ['rd', 'rs1', 'rs2']
arg_select.next = get_arg_select(arg_list)
# FENCE and FENCE.I instructions
elif instruction_family == '00011':
funct3.next = get_arg(instruction, 'funct3')
funct7.next = intbv(0)
rs1.next = intbv(0)
rs2.next = intbv(0)
rd.next = intbv(0)
imm12.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = intbv(0)
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
arg_list = []
arg_select.next = get_arg_select(arg_list)
# Load Instructions
elif instruction_family == '00000':
funct3.next = get_arg(instruction, 'funct3')
funct7.next = intbv(0)
rs1.next = get_arg(instruction, 'rs1')
rd.next = get_arg(instruction,'rd')
imm12.next = get_arg(instruction,'imm12')
rs2.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = intbv(0)
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
arg_list = ['rs1', 'rd', 'imm12']
arg_select.next = get_arg_select(arg_list)
# Store Instructions
elif instruction_family == '01000':
funct3.next = get_arg(instruction, 'funct3')
funct7.next = intbv(0)
rs1.next = get_arg(instruction, 'rs1')
rs2.next = get_arg(instruction,'rs2')
imm12.next = get_arg(instruction,'imm12_sb')
rd.next = intbv(0)
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = intbv(0)
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
arg_list = ['rs1', 'rs2', 'imm12']
arg_select.next = get_arg_select(arg_list)
# System Instructions
elif instruction_family == '11100':
funct3.next = get_arg(instruction, 'funct3')
funct7.next = intbv(0)
rs1.next = intbv(0)
rs2.next = intbv(0)
imm12.next = get_arg(instruction, 'imm12')
imm12lo.next = intbv(0)
imm12hi.next = intbv(0)
imm20.next = intbv(0)
shamt.next = intbv(0)
shamtw.next = intbv(0)
rm.next = intbv(0)
if get_arg(instruction, 'funct3') == 0:
rd.next = intbv(0)
arg_list = ['imm12']
arg_select.next = get_arg_select(arg_list)
else:
rd.next = get_arg(instruction, 'rd')
arg_list = ['rd', 'imm12']
arg_select.next = get_arg_select(arg_list)
def stimulus():
for i in range(2**width):
B.next = intbv(i)
yield delay(10)
print("B: " + bin(B, width) + "| G: " + bin(G, width))
def stimulus():
for i in range(2**WIDTH):
bin_i.next = intbv(i)
yield delay(10)
print("bin_i {0} | gray_o {1}".format(bin(bin_i, WIDTH), bin(gray_o, WIDTH)))
def stimulus(B, G, n):
for i in range(2**n):
B.next = intbv(i)
yield delay(10)
Rn.append(bin(G, width=n))
def stimulus():
# Test Branch Instructions
branch_instr = ['beq','bne','blt','bge','bltu','bgeu']
for i in range(len(branch_instr)):
instruction.next = intbv(int(test_instruction[branch_instr[i]],2))[32:]
yield delay(10)
assert(bin(rs1, width=5) == '00010')
assert(bin(rs2, width=5) == '00001')
assert(bin(imm12lo, width=6) == '010000')
assert(bin(imm12hi, width=6) == '000000')
assert(bin(opcode, width=7) == '1100011')
assert(bin(arg_select, width=10) == '1100110000')
if i < 2:
assert(bin(funct3, width=3) == bin(i, width=3))
else:
assert(bin(funct3, width=3) == bin(i+2, width=3))
# Test LUI and AUIPC Instructions
lui_auipc_instr = ['lui', 'auipc']
for i in range(len(lui_auipc_instr)):
instruction.next = intbv(int(test_instruction[lui_auipc_instr[i]],2))[32:]
yield delay(10)
assert(bin(rd, width=5) == '00001')
assert(bin(arg_select, width=10) == '0010000100')
assert(bin(imm20, width=20) == '00000000000000000001')
if i == 0:
assert(bin(opcode, width=7) == '0110111')
else:
assert(bin(opcode, width=7) == '0010111')
# Test Jump Instructions
jump_instr = ['jalr', 'jal']
for i in range(len(jump_instr)):
instruction.next = intbv(int(test_instruction[jump_instr[i]],2))[32:]
yield delay(10)
assert(bin(rd, width=5) == '00001')
if i == 0:
assert(bin(imm12, width=12) == '000000000001')
assert(bin(rs1, width=5) == '00001')
assert(bin(arg_select, width=10) == '1010001000')
assert(bin(opcode, width=7) == '1100111')
else:
assert(bin(imm20, width=20) == '10001100010000000001')
assert(bin(arg_select, width=10) == '0010000100')
assert(bin(opcode, width=7) == '1101111')
# Test Addition and Logical immediate Instructions
arith_logic_imm_instr = ['addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi']
for i in range(len(arith_logic_imm_instr)):
instruction.next = intbv(int(test_instruction[arith_logic_imm_instr[i]],2))[32:]
yield delay(10)
assert(bin(rd, width=5) == '00001')
assert(bin(rs1, width=5) == '00001')
assert(bin(opcode, width=7) == '0010011')
if i in [1,5,6]:
assert(bin(arg_select, width=10) == '1010000010')
assert(bin(shamt, width=5) == '00001')
else:
assert(bin(imm12, width=12) == '000000000001')
assert(bin(arg_select, width=10) == '1010001000')
# Test Addition and Logical Reg to Reg Instructions
arith_logic_r2r_instr = ['add', 'sll', 'slt', 'sltu', 'xor', 'srl', 'or', 'and', 'sub', 'sra']
for i in range(len(arith_logic_r2r_instr)):
instruction.next = intbv(int(test_instruction[arith_logic_r2r_instr[i]],2))[32:]
yield delay(10)
assert(bin(rd, width=5) == '00011')
assert(bin(rs1, width=5) == '00001')
assert(bin(rs2, width=5) == '00010')
assert(bin(opcode, width=7) == '0110011')
assert(bin(arg_select, width=10) == '1110000000')
if i == 8:
assert(bin(funct3, width=3) == bin(0, width=3))
elif i == 9:
assert(bin(funct3, width=3) == bin(5, width=3))
else :
assert(bin(funct3, width=3) == bin(i, width=3))
# Test Load Instructions
load_instr = ['lb', 'lh', 'lw', 'lbu', 'lhu']
for i in range(len(load_instr)):
instruction.next = intbv(int(test_instruction[load_instr[i]],2))[32:]
yield delay(10)
assert(bin(rd, width=5) == '00010')
assert(bin(rs1, width=5) == '00001')
assert(bin(imm12, width=12) == '000000000001')
assert(bin(opcode, width=7) == '0000011')
assert(bin(arg_select, width=10) == '1010001000')
if i <= 2:
assert(bin(funct3, width=3) == bin(i, width=3))
else:
assert(bin(funct3, width=3) == bin(i+1, width=3))
# Test Store Instructions
store_instr = ['sb', 'sh', 'sw']
for i in range(len(store_instr)):
instruction.next = intbv(int(test_instruction[store_instr[i]],2))[32:]
yield delay(10)
assert(bin(rs1, width=5) == '00010')
assert(bin(rs2, width=5) == '00001')
assert(bin(imm12, width=12) == '000001000001')
assert(bin(opcode, width=7) == '0100011')
assert(bin(arg_select, width=10) == '1100001000')
assert(bin(funct3, width=3) == bin(i, width=3))
# Test System Instructions
sys_instr = ['ecall', 'ebreak', 'rdcycle', 'rdcycleh', 'rdtime', 'rdtimeh', 'rdinstret', 'rdinstreth']
for i in range(len(sys_instr)):
instruction.next = intbv(int(test_instruction[sys_instr[i]],2))[32:]
yield delay(10)
assert(bin(opcode, width=7) == '1110011')
if i in [0,1]:
assert(bin(arg_select, width=10) == '0000001000')
assert(bin(funct3, width=3) == bin(0, width=3))
assert(bin(imm12, width=12) == bin(i, width=12))
else:
assert(bin(arg_select, width=10) == '0010001000')
assert(bin(funct3, width=3) == bin(2, width=3))
assert(bin(rd, width=5) == '00001')
sys_imms = ['110000000000', '110010000000',
'110000000001', '110010000001',
'110000000010', '110010000010']
assert(bin(imm12, width=12) == sys_imms[i-2])
