def read_rc_ports(expected_datas):
""" Read all rc ports in one SPI transfer and compare the result bytes to expected_datas """
print 'read all rc ports at once...',
master_to_slave = get_read_rc_port_command(4)
for i in downrange(4, 1):
master_to_slave = concat(master_to_slave, get_read_rc_port_command(i))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
for i in downrange(5, 1):
self.assertEquals(slave_to_master[i*32-16:(i-1)*32].signed(), expected_datas[i])
print 'done'
def read_ext_ports(expected_datas):
""" Read all ext ports in one SPI transfer and compare the result bytes to expected_datas """
print 'read all ext ports at once...',
master_to_slave = get_read_ext_port_command(7)
for i in downrange(7, 1):
master_to_slave = concat(master_to_slave, get_read_ext_port_command(i))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
for i in downrange(8, 1):
self.assertEquals(slave_to_master[i*24-16:(i-1)*24], expected_datas[i])
print 'done'
def read_ext_ports(expected_datas):
""" Read all ext ports in one SPI transfer and compare the result bytes to expected_datas """
print 'read all ext ports at once...',
master_to_slave = get_read_ext_port_command(7)
for i in downrange(7, 1):
master_to_slave = concat(master_to_slave,
get_read_ext_port_command(i))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
for i in downrange(8, 1):
self.assertEquals(slave_to_master[i * 24 - 16:(i - 1) * 24],
expected_datas[i])
print 'done'
def read_rc_ports(expected_datas):
""" Read all rc ports in one SPI transfer and compare the result bytes to expected_datas """
print 'read all rc ports at once...',
master_to_slave = get_read_rc_port_command(4)
for i in downrange(4, 1):
master_to_slave = concat(master_to_slave,
get_read_rc_port_command(i))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
for i in downrange(5, 1):
self.assertEquals(
slave_to_master[i * 32 - 16:(i - 1) * 32].signed(),
expected_datas[i])
print 'done'
def fake_mcp3008(channel, values):
"""
Send data like an MCP3008 would
CPOL=1 and CPHA=1 here:
- the base value of the clock is HIGH
- data is captured on the clock's rising edge and data is
propagated on a falling edge.
"""
yield adc1_cs.negedge
# wait for start bit: first clock with mosi high
while adc1_mosi == LOW:
yield adc1_clk.posedge
self.assertEqual(adc1_mosi, HIGH)
# single-ended bit
yield adc1_clk.posedge
self.assertEqual(adc1_mosi, HIGH)
# channel bits
for i in downrange(len(channel)):
yield adc1_clk.posedge
channel[i] = adc1_mosi
print 'master wants channel:', channel
# one more bit for conversion
yield adc1_clk.posedge
# then MCP3008 sends a null byte
yield adc1_clk.negedge
adc1_miso.next = LOW
# and then the 10-bit value
value = values[channel]
print 'slave sending:', value
for i in downrange(len(value)):
yield adc1_clk.negedge
adc1_miso.next = value[i]
yield adc1_cs.posedge
print "slave done"
def spi_slave(channel, values):
"""
Send data like an MCP3008 would
CPOL=1 and CPHA=1 here:
- the base value of the clock is HIGH
- data is captured on the clock's rising edge and data is
propagated on a falling edge.
"""
yield spi_ss_n.negedge
# wait for start bit: first clock with mosi high
while spi_mosi == LOW:
yield spi_clk.posedge
self.assertEqual(spi_mosi, HIGH)
# single-ended bit
yield spi_clk.posedge
self.assertEqual(spi_mosi, HIGH)
# channel bits
for i in downrange(len(channel)):
yield spi_clk.posedge
channel[i] = spi_mosi
print 'master wants channel:', channel
# one more bit for conversion
yield spi_clk.posedge
# then MCP3008 sends a null byte
yield spi_clk.negedge
spi_miso.next = LOW
# and then the 10-bit value
value = values[channel]
print 'slave sending:', value
for i in downrange(len(value)):
yield spi_clk.negedge
spi_miso.next = value[i]
yield spi_ss_n.posedge
print "slave done"
def set_servos_consigns(consigns):
""" Set all servos consigns in one SPI transfer """
print 'set all servos'
master_to_slave = get_write_servo_command(8, consigns[8])
for i in downrange(8, 1):
master_to_slave = concat(master_to_slave, get_write_servo_command(i, consigns[i]))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
print 'done'
def set_motors_speeds(speeds):
""" Set all motors speeds in one SPI transfer """
print 'set all motors'
master_to_slave = get_write_motor_command(8, speeds[8])
for i in downrange(8, 1):
master_to_slave = concat(master_to_slave, get_write_motor_command(i, speeds[i]))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
print 'done'
def set_servos_consigns(consigns):
""" Set all servos consigns in one SPI transfer """
print 'set all servos'
master_to_slave = get_write_servo_command(8, consigns[8])
for i in downrange(8, 1):
master_to_slave = concat(
master_to_slave, get_write_servo_command(i, consigns[i]))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
print 'done'
def set_motors_speeds(speeds):
""" Set all motors speeds in one SPI transfer """
print 'set all motors'
master_to_slave = get_write_motor_command(8, speeds[8])
for i in downrange(8, 1):
master_to_slave = concat(master_to_slave,
get_write_motor_command(i, speeds[i]))
slave_to_master = intbv(0)
yield spi_transfer(master_to_slave, slave_to_master)
print 'done'
def spi_transfer(master_to_slave, slave_to_master):
""" Send data like an SPI master would """
yield delay(50)
sspi_cs.next = LOW
yield delay(10)
for i in downrange(len(master_to_slave)):
sspi_clk.next = HIGH
sspi_mosi.next = master_to_slave[i]
yield delay(10)
sspi_clk.next = LOW
slave_to_master[i] = sspi_miso
yield delay(10)
sspi_cs.next = HIGH
def spi_transfer(miso, mosi, sclk, ss_n, master_to_slave, slave_to_master):
""" Send data like an SPI master would """
yield delay(50)
ss_n.next = LOW
yield delay(10)
for i in downrange(len(master_to_slave)):
sclk.next = 1
mosi.next = master_to_slave[i]
yield delay(10)
sclk.next = 0
slave_to_master[i] = miso
yield delay(10)
ss_n.next = HIGH
def spi_transfer(master_to_slave, slave_to_master):
""" Send data like an SPI master would """
yield delay(50)
sspi_cs.next = LOW
yield delay(10)
for i in downrange(len(master_to_slave)):
sspi_clk.next = HIGH
sspi_mosi.next = master_to_slave[i]
yield delay(10)
sspi_clk.next = LOW
slave_to_master[i] = sspi_miso
yield delay(10)
sspi_cs.next = HIGH
def spi_transfer(miso, mosi, sclk, ss_n, master_to_slave, slave_to_master):
""" Send data like an SPI master would """
yield delay(50)
ss_n.next = LOW
yield delay(10)
for i in downrange(len(master_to_slave)):
sclk.next = 1
mosi.next = master_to_slave[i]
yield delay(10)
sclk.next = 0
slave_to_master[i] = miso
yield delay(10)
ss_n.next = HIGH
def Tester(self, miso, mosi, sclk, ss_n, key, length, master_read_n,
value_for_master, master_write_n, value_from_master, clk,
rst_n):
master_to_slave = intbv(0)
slave_to_master = intbv(0)
def check_write():
""" Check that what the SPI slave read corresponds to sent data """
yield master_write_n.negedge
n = len(self.master_to_slave)
# print 'master sent', n, 'bytes'
# print 'slave read key:', hex(key)
self.assertEqual(key, self.master_to_slave[n:n - 8])
# print 'slave read length:', hex(length)
self.assertEqual(length, self.master_to_slave[n - 8:n - 16])
if length > 0:
# print 'slave should have read value:', hex(self.master_to_slave[n-16:])
self.assertEqual(value_from_master[length * 8:],
self.master_to_slave[n - 16:])
def check_read():
""" Check that what the SPI slave sent corresponds to expected data """
yield master_read_n.negedge
n = len(self.master_to_slave)
# print 'master sent', n, 'bytes'
# print 'slave read key:', hex(key)
self.assertEqual(key, self.master_to_slave[n:n - 8])
# print 'slave read length:', hex(length)
self.assertEqual(length, self.master_to_slave[n - 8:n - 16])
if length > 0:
# print 'slave ask for', length, 'bytes to send them to master'
value_for_master.next[length * 8:] = randrange(256 * length)
# Wait for end of transfer
yield ss_n.posedge
if length > 0:
# print 'slave sent value:', hex(value_for_master[length*8:])
self.assertEqual(value_for_master[length * 8:],
self.slave_to_master[n - 16:])
# Send write commands with values from 0 to 8 bytes
for i in range(10):
self.master_to_slave = random_write(i)
self.slave_to_master = intbv(0)
# print "\nwrite test", 'master sends:', hex(self.master_to_slave)
yield join(
spi_transfer(miso, mosi, sclk, ss_n, self.master_to_slave,
self.slave_to_master), check_write())
# print 'slave responded:', hex(self.slave_to_master)
# Send write commands with values from 8 to 0 bytes
for i in downrange(10):
self.master_to_slave = random_write(i)
self.slave_to_master = intbv(0)
# print "\nwrite test", 'master sends:', hex(self.master_to_slave)
yield join(
spi_transfer(miso, mosi, sclk, ss_n, self.master_to_slave,
self.slave_to_master), check_write())
# print 'slave responded:', hex(self.slave_to_master)
# Send read commands with values from 0 to 8 bytes
for i in range(10):
self.master_to_slave = random_read(i)
self.slave_to_master = intbv(0)
# print "\nread test", 'master sends:', hex(self.master_to_slave)
yield join(
spi_transfer(miso, mosi, sclk, ss_n, self.master_to_slave,
self.slave_to_master), check_read())
# print 'slave responded:', hex(self.slave_to_master)
# Send read commands with values from 8 to 0 bytes
for i in downrange(10):
self.master_to_slave = random_read(i)
self.slave_to_master = intbv(0)
# print "\nread test", 'master sends:', hex(self.master_to_slave)
yield join(
spi_transfer(miso, mosi, sclk, ss_n, self.master_to_slave,
self.slave_to_master), check_read())
# print 'slave responded:', hex(self.slave_to_master)
print 'DONE'
raise StopSimulation()