def make_vertices(self, model, n_steps): # TODO remove n_steps
"""Construct the data which can be loaded into the memory of a
SpiNNaker machine.
"""
# Extract all the filters from the incoming connections to build the
# filter regions.
signals_conns = model.get_signals_to_object(self)[InputPort.standard]
self.filter_region, self.filter_routing_region = make_filter_regions(
signals_conns, model.dt, True, model.keyspaces.filter_routing_tag)
# Use a matrix region to record into (slightly unpleasant)
self.recording_region = regions.MatrixRegion(
np.zeros((self.size_in, n_steps), dtype=np.uint32))
# This isn't partitioned, so we just compute the SDRAM requirement and
# return a new vertex.
self.system_region = SystemRegion(model.machine_timestep, self.size_in)
self.regions = [None] * 15
self.regions[0] = self.system_region
self.regions[1] = self.filter_region
self.regions[2] = self.filter_routing_region
self.regions[14] = self.recording_region # **YUCK**
resources = {
Cores: 1,
SDRAM: regions.utils.sizeof_regions(self.regions, None)
}
self.vertex = Vertex(get_application("value_sink"), resources)
# Return the spec
return netlistspec(self.vertex,
self.load_to_machine,
after_simulation_function=self.after_simulation)
def make_vertices(self, model, n_steps):
"""Create the vertices to be simulated on the machine."""
# Create the system region
self.system_region = SystemRegion(model.machine_timestep,
self.period is not None, n_steps)
# Get all the outgoing signals to determine how big the size out is and
# to build a list of keys.
sigs_conns = model.get_signals_from_object(self)
if len(sigs_conns) == 0:
return netlistspec([])
keys = list()
self.transmission_parameters = list()
for sig, transmission_params in sigs_conns[OutputPort.standard]:
# Add the keys for this connection
transform, sig_keys = get_transform_keys(sig, transmission_params)
keys.extend(sig_keys)
self.transmission_parameters.append((transmission_params,
transform))
size_out = len(keys)
# Build the keys region
self.keys_region = regions.KeyspacesRegion(
keys, [regions.KeyField({"cluster": "cluster"})],
partitioned_by_atom=True
)
# Create the output region
self.output_region = regions.MatrixRegion(
np.zeros((n_steps, size_out)),
sliced_dimension=regions.MatrixPartitioning.columns
)
self.regions = [self.system_region, self.keys_region,
self.output_region]
# Partition by output dimension to create vertices
transmit_constraint = partition.Constraint(10)
sdram_constraint = partition.Constraint(8*2**20) # Max 8MiB
constraints = {
transmit_constraint: lambda s: s.stop - s.start,
sdram_constraint: (
lambda s: regions.utils.sizeof_regions(self.regions, s)),
}
for sl in partition.partition(slice(0, size_out), constraints):
# Determine the resources
resources = {
Cores: 1,
SDRAM: regions.utils.sizeof_regions(self.regions, sl),
}
vsl = VertexSlice(sl, self._label, get_application("value_source"),
resources)
self.vertices.append(vsl)
# Return the vertices and callback methods
return netlistspec(self.vertices, self.load_to_machine,
self.before_simulation)
def make_vertices(self, output_signals, machine_timestep, filter_region,
filter_routing_region):
"""Partition the transform matrix into groups of rows and assign each
group of rows to a core for computation.
If the group needs to be split over multiple chips (i.e., the group is
larger than 17 cores) then partition the matrix such that any used
chips are used in their entirety.
"""
if OutputPort.standard not in output_signals:
self.cores = list()
else:
# Get the output transform, keys and slices for this slice of the
# filter.
transform, keys, output_slices = \
get_transforms_and_keys(output_signals[OutputPort.standard],
self.column_slice)
size_out = transform.shape[0]
# Build as many vertices as required to keep the number of rows
# handled by each core below max_rows.
n_cores = ((size_out // self.max_rows) +
(1 if size_out % self.max_rows else 0))
# Build the transform region for these cores
transform_region = regions.MatrixRegion(
np_to_fix(transform),
sliced_dimension=regions.MatrixPartitioning.rows)
# Build all the vertices
self.cores = [
FilterCore(self._label, self.column_slice, out_slice,
transform_region, keys, output_slices,
machine_timestep, filter_region,
filter_routing_region)
for out_slice in divide_slice(slice(0, size_out), n_cores)
]
return self.cores
def make_vertices(self, model, n_steps):
"""Make vertices for the filter."""
# Get the outgoing transforms and keys
sigs = model.get_signals_from_object(self)
if OutputPort.standard in sigs:
outgoing = sigs[OutputPort.standard]
transform, output_keys, sigs_pars_slices = \
get_transforms_and_keys(outgoing)
else:
transform = np.array([[]])
output_keys = list()
sigs_pars_slices = list()
size_out = len(output_keys)
# Calculate how many cores and chips to use.
if self.n_cores_per_chip is None or self.n_chips is None:
# The number of cores is largely a function of the input size, we
# try to ensure that each core is receiving a max of 32 packets per
# timestep.
n_cores_per_chip = int(min(16, np.ceil(self.size_in / 32.0)))
# The number of chips is now determined by the size in (columns in
# the transform matrix), the size out (rows in the transform
# matrix) and the number of cores per chip.
n_chips = self.n_chips or 1
n_cores = n_chips * n_cores_per_chip
while True:
rows_per_core = int(
np.ceil(float(size_out) / (n_cores * n_chips)))
load_per_core = rows_per_core * self.size_in
# The 8,000 limits the number of columns in each row that we
# need to process. This is a heuristic.
if load_per_core <= 8000 or n_chips > 9:
# The load per core is acceptable or we're using way too
# many chips
break
if n_cores < 16:
# Increase the number of cores per chip if we can
n_cores += 1
else:
# Otherwise increase the number of chips
n_chips += 1
# Store the result
self.n_cores_per_chip = n_cores
self.n_chips = n_chips
# Slice the input space into the given number of subspaces, this is
# repeated on each chip.
input_slices = list(
divide_slice(slice(0, self.size_in), self.n_cores_per_chip))
# Slice the output space into the given number of subspaces, this is
# sliced across all of the chips.
output_slices = divide_slice(slice(0, size_out),
self.n_cores_per_chip * self.n_chips)
# Construct the output keys and transform regions; the output keys and
# sliced, and the transform is sliced by rows.
self.output_keys_region = regions.KeyspacesRegion(
output_keys,
fields=[regions.KeyField({'cluster': 'cluster'})],
partitioned_by_atom=True)
self.transform_region = regions.MatrixRegion(
np_to_fix(transform),
sliced_dimension=regions.MatrixPartitioning.rows)
# Construct the system region
self.system_region = SystemRegion(self.size_in, model.machine_timestep)
# Get the incoming filters
incoming = model.get_signals_to_object(self)
self.filters_region, self.routing_region = make_filter_regions(
incoming[InputPort.standard],
model.dt,
True,
model.keyspaces.filter_routing_tag,
width=self.size_in)
# Make the vertices and constraints
iter_output_slices = iter(output_slices)
cons = list() # List of constraints
# For each chip that we'll be using
for _ in range(self.n_chips):
chip_vertices = list()
# Each core is given an input slice and an output slice. The same
# set of input slices is used per chip, but we iterate through the
# whole list of output slices.
for in_slice, out_slice in zip(input_slices, iter_output_slices):
# Determine the amount of SDRAM required (the 24 additional
# bytes are for the application pointer table). We also
# include this cores contribution to a shared SDRAM vector.
sdram = (24 + 4 * (in_slice.stop - in_slice.start) +
self.system_region.sizeof() +
self.filters_region.sizeof_padded() +
self.routing_region.sizeof_padded() +
self.output_keys_region.sizeof_padded(out_slice) +
self.transform_region.sizeof_padded(out_slice))
# Create the vertex and include in the list of vertices
v = ParallelFilterSlice(in_slice, out_slice, {
Cores: 1,
SDRAM: sdram
}, sigs_pars_slices)
chip_vertices.append(v)
self.vertices.append(v)
# Create a constraint which will force all of the vertices to exist
# of the same chip.
cons.append(SameChipConstraint(chip_vertices))
# Return the spec
return netlistspec(self.vertices,
self.load_to_machine,
constraints=cons)
def before_simulation(self, netlist, simulator, n_steps):
"""Generate the values to output for the next set of simulation steps.
"""
# Write out the system region to deal with the current run-time
self.system_region.n_steps = n_steps
# Evaluate the node for this period of time
if self.period is not None:
max_n = min(n_steps, int(np.ceil(self.period / simulator.dt)))
else:
max_n = n_steps
ts = np.arange(simulator.steps, simulator.steps + max_n) * simulator.dt
if callable(self.function):
values = np.array([self.function(t) for t in ts])
elif isinstance(self.function, Process):
values = self.function.run_steps(max_n, d=self.size_out,
dt=simulator.dt)
else:
values = np.array([self.function for t in ts])
# Ensure that the values can be sliced, regardless of how they were
# generated.
values = npext.array(values, min_dims=2)
# Compute the output for each connection
outputs = []
for transmission_params, transform in self.transmission_parameters:
output = []
# For each f(t) for the next set of simulations we calculate the
# output at the end of the connection. To do this we first apply
# the pre-slice, then the function and then the post-slice.
for v in values:
# Apply the pre-slice
v = v[transmission_params.pre_slice]
# Apply the function on the connection, if there is one.
if transmission_params.function is not None:
v = np.asarray(transmission_params.function(v),
dtype=float)
output.append(np.dot(transform, v.T))
outputs.append(np.array(output).reshape(max_n, -1))
# Combine all of the output values to form a large matrix which we can
# dump into memory.
output_matrix = np.hstack(outputs)
new_output_region = regions.MatrixRegion(
np_to_fix(output_matrix),
sliced_dimension=regions.MatrixPartitioning.columns
)
# Write the simulation values into memory
for vertex in self.vertices:
self.vertices_region_memory[vertex][self.system_region].seek(0)
self.system_region.n_steps = max_n
self.system_region.write_subregion_to_file(
self.vertices_region_memory[vertex][self.system_region],
vertex.slice
)
self.vertices_region_memory[vertex][self.output_region].seek(0)
new_output_region.write_subregion_to_file(
self.vertices_region_memory[vertex][self.output_region],
vertex.slice
)