def main():
Ns = np.array([0, 8, 7], dtype=np.int32)
scb = Scoreboard()
test = scb.GetTest("test")
golden = np.concatenate([np.arange(N + 1, dtype=np.int32)
for N in Ns])[:, np.newaxis]
st = Stacker(n=golden.shape[0], callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
test.Expect((golden, ))
yield rst_out_ev
master = TwoWire.Master(irdy, iack, i, ck_ev)
slave = TwoWire.Slave(ordy, oack, o, ck_ev, callbacks=[bg.Get])
values = master.values
def it():
for N in Ns:
values[0][0] = N
yield values
yield from master.SendIter(it())
# for i in range(100):
# yield ck_ev
yield from repeat(ck_ev, 100)
FinishSim()
def main():
# prepare golden data
# N = 50 is the total number of object
# input_golden size = (50,6,3)
# input_golden[0,1,:] = 1th point's [X,Y,R] for 0th obj
#
# is_inside_golden size = (50,1)
# input_golden[0,:6,:] is the input needed for is_inside_golden[0]
with open('../grad.data') as f:
golden = f.readlines()
golden = np.char.rstrip(golden).reshape(-1,7)
N = golden.shape[0]
is_inside_golden = np.stack(np.char.split(golden[:,0]," "),axis=1)[-1].astype(np.int32).reshape(-1,1)
input_golden = np.stack(np.char.split(golden[:,1:].reshape(-1)," "),axis=0).astype(np.int32).reshape(-1,6,3)
# 1. Connect to Verilog
# TODO
# 2. Construct events
# TODO
# 3. Initialization
# Mostly you only need to change the size of Stacker
scb = Scoreboard("Geofence")
test = scb.GetTest("is_inside")
st = Stacker(N, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
# 4. Construct master (driver) and slave (monitor) and
# connect slave to the scoreboard.
# hint:
# TODO
def custom_master():
pass
# 5. Expect golden pattern for GetTest.
# This create a tuple of N.
# TODO
test.Expect((is_inside_golden,))
# 6. start simulation
# Wait 1 extra cycle after reset
yield rst_out_ev # wait for reset
yield ck_ev # wait one more cycle
# Now start sending X,Y,R
# hint: yield from custom_master()
# TODO
# 7. end simulation after sending all the data
# check if the number of results matches the number of golden
assert st.is_clean
FinishSim()
def main():
# Calculate answer
N_TEST = 100
N_ANS = 100 >> 1
gold_in = np.random.randint(256, size=N_TEST, dtype=np.int32)
gold_out = M.Downsample(gold_in)
# Connect to Verilog
(
irdy,
iack,
ordy,
oack,
idata,
odata,
) = CreateBuses([
(("dut", "i_rdy"), ),
(("dut", "i_ack"), ),
(("dut", "o_rdy"), ),
(("dut", "o_ack"), ),
(("dut", "i_data"), ),
(("dut", "o_data"), ),
])
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
scb = Scoreboard("Counter")
test = scb.GetTest("Counter")
st = Stacker(N_ANS, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
master = TwoWire.Master(irdy, iack, idata, ck_ev, A=1, B=2)
slave = TwoWire.Slave(ordy,
oack,
odata,
ck_ev,
A=1,
B=2,
callbacks=[bg.Get])
mdata = master.values
test.Expect((gold_out[:, np.newaxis], ))
# start simulation
yield rst_out_ev
yield ck_ev
def Iter():
for i in gold_in:
mdata.i_data[0] = i
yield mdata
yield from master.SendIter(Iter())
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
scb = Scoreboard("RemapCache")
test = scb.GetTest(f"test{RMC_CONF}")
st = Stacker(0,
callbacks=[
lambda mat: npd.savetxt("rmc_got.txt", mat[0], fmt="%d"),
test.Get
])
bg = BusGetter(callbacks=[st.Get])
wad_master = OneWire.Master(wad_dval_bus, wad_bus, ck_ev)
ra_master = TwoWire.Master(ra_rdy_bus, ra_ack_bus, ra_bus, ck_ev)
rd_slave = TwoWire.Slave(rd_rdy_bus,
rd_ack_bus,
rd_bus,
ck_ev,
callbacks=[bg.Get])
wad_data = wad_master.values
ra_data = ra_master.values
yield rst_out_ev
# start simulation
npd.copyto(cfg_bus.values.i_xor_srcs[0], xsrc)
cfg_bus.values.i_xor_swaps[0] = xswap
cfg_bus.Write()
yield ck_ev
def IterWrite():
for i in range(N_VEC):
wad_data[0][0] = 0
wad_data[1][0] = i
npd.copyto(wad_data[2], npi.arange(i * VSIZE, (i + 1) * VSIZE))
yield wad_data
yield from wad_master.SendIter(IterWrite())
for i in range(10):
yield ck_ev
NTEST = N_VEC * VSIZE - npd.sum(stride, dtype=npd.int32) - 1
raddr = npi.arange(NTEST)[:, newaxis] + STEP
st.Resize(NTEST)
test.Expect((raddr, ))
def IterRead():
for i in raddr:
ra_data[0][0] = 0
npd.copyto(ra_data[1], i)
yield ra_data
yield from ra_master.SendIter(IterRead())
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
n_golden, bofs = cfg.CreateBlockTransaction()
scb = Scoreboard("ParallelBlockLooper_mc")
test_b = scb.GetTest("bofs")
# master
master = TwoWire.Master(rdy_bus_s, ack_bus_s, bus_s, ck_ev)
i_data = master.values
# slave
ans = [deque() for _ in range(N_TAU)]
bgs_b = list()
masters_bdone = list()
resps = list()
slaves_b = list()
for i in range(N_TAU):
bg_b = BusGetter(copy=True,
callbacks=[lambda x, i=i: ans[i].append(x)])
master_bdone = OneWire.Master(dval_buss[i], tuple(), ck_ev)
resp = Response(master_bdone.SendIter, ck_ev, B=100)
slave_b = TwoWire.Slave(
rdy_buss_b[i],
ack_buss_b[i],
buss_b[i],
ck_ev,
callbacks=[bg_b.Get, lambda x, resp=resp: resp.Append(tuple())],
A=1,
B=100)
bgs_b.append(bg_b)
masters_bdone.append(masters_bdone)
resps.append(resp)
slaves_b.append(slave_b)
yield rst_out_ev
yield ck_ev
# start simulation
npd.copyto(i_data[0], cfg.pcfg['local'][0])
npd.copyto(i_data[1], cfg.pcfg['end'][0])
yield from master.Send(i_data)
for i in range(30):
yield ck_ev
for i in range(n_golden):
b = bofs[i]
popped = False
for a in ans:
if a and (a[0] == b).all():
a.popleft()
popped = True
if popped:
break
assert popped, f"No correct bofs to match {b}"
assert all(not a for a in ans), "Some extra bofs"
FinishSim()
def main():
# Calculate answer
# See MyModel.py for more information.
images = M.LoadImages()
features = M.ComputeImages(images)
tags = [feature[4] for feature in features]
answer = np.array(M.SortFeatures(features), dtype=np.int32)
N_IMG = 16
N_PX = 120*80
# Connect to Verilog
# Connect to the Verilog wire (please see the document)
# TODO
# Construct clock and reset event
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
# Mostly you only need to change the size of Stacker
scb = Scoreboard("ISE")
test = scb.GetTest(f"Top")
st = Stacker(N_IMG, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
# Construct master (driver) and slave (monitor) and
# connect slave to the scoreboard.
# Choose to use OneWire or TwoWire accordingly.
# TODO
# NOTE: Construct your master with A=1, B=1 to send data in every cycle.
# Extract the data bus of master
# For creating the iterator (see Iter() below) easily.
# TODO
# Check the data at slave.
# This create a tuple of two column vectors of size 16.
# tag, type
# TODO
# Start simulation
# Wait 1 extra cycle after reset
yield rst_out_ev
yield ck_ev
# Then send to the DUT.
# NOTE: DO NOT set latency.
# Use an iterator to set the mdata construted above.
# Wait 100 cycles and Finish
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
seed = np.random.randint(10000)
print("Seed for this run is {}".format(seed))
np.random.seed(seed)
N = 100
golden = np.random.randint(100, size=(N, 1))
scb = Scoreboard("Controller")
test = scb.GetTest("Forward" if getenv("SLOW") is None else "ForwardSlow")
st = Stacker(N, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
(
srdy,
sack,
sdata,
drdy,
dack,
ddata,
) = CreateBuses([
("src_rdy", ),
("src_ack", ),
("src_data", ),
("dst_rdy", ),
("dst_canack", ),
("dst_data", ),
])
master = TwoWire.Master(srdy, sack, sdata, ck_ev, A=5, B=8)
slave = TwoWire.Slave(drdy,
dack,
ddata,
ck_ev,
callbacks=[bg.Get],
A=4,
B=8)
yield rst_out_ev
yield ck_ev
def It():
sv = sdata.values
for i in golden.flat:
sv[0][0] = i
yield sv
test.Expect((golden, ))
yield from master.SendIter(It())
for i in range(10):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
N = 10
scb = Scoreboard()
test = scb.GetTest("ahb", ne=op.ne, max_err=10)
bg = BusGetter(callbacks=[test.Get])
ms = Ahb.Master(hsel, haddr, hwrite, htrans, hsize, hburst, hready, hresp,
rd, wd, ck_ev)
yield rs_ev
for i in range(10):
yield ck_ev
def rng(magic):
while True:
magic = (magic * 199 + 12345) & 65535
yield magic
r = rng(25251)
MAGIC = next(r)
ADR = 0
print("Test Single R/W\n" f"MAGIC/ADR is {MAGIC}/{ADR}")
test.Expect(MAGIC)
yield from ms.Write(ADR, MAGIC)
read_v = yield from ms.Read(ADR)
test.Get(read_v)
yield ck_ev
MAGIC = next(r)
ADR = 100
print("Test Pipelined R/W\n" f"MAGIC/ADR is {MAGIC}/{ADR}")
wcmd = [(True, ADR + i * 4, MAGIC + i) for i in range(N)]
rcmd = [(False, ADR + i * 4) for i in range(N)]
test.Expect([MAGIC + i for i in range(N)])
read_v = yield from ms.IssueCommands(wcmd + rcmd)
test.Get(read_v)
yield ck_ev
MAGIC = next(r)
ADR = 200
print("Test Pipelined Interleaved R/W\n" f"MAGIC/ADR is {MAGIC}/{ADR}")
wcmd = [(True, ADR + i * 4, MAGIC + i) for i in range(N)]
rcmd = [(False, ADR + i * 4) for i in range(N)]
cmd = [v for p in zip(wcmd, rcmd) for v in p]
test.Expect([MAGIC + i for i in range(N)])
read_v = yield from ms.IssueCommands(cmd)
test.Get(read_v)
for i in range(10):
yield ck_ev
def main():
scb = Scoreboard("ChunkAddrLooper")
test = scb.GetTest("test")
st = Stacker(0, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
master = TwoWire.Master(mrdy_bus, mack_bus, mofs_bus, ck_ev)
i_data = master.values
slave = TwoWire.Slave(crdy_bus,
cack_bus,
cmd_bus,
ck_ev,
callbacks=[bg.Get])
yield rst_out_ev
# simulation
n_bofs, bofs = cfg.CreateBlockTransaction()
TEST0 = not getenv("TEST0") is None
print(f"Testing {0 if TEST0 else 1}...")
TEST_UMCFG = cfg.umcfg_i0 if TEST0 else cfg.umcfg_i1
OFS = int(bool(TEST0))
for i in range(n_bofs):
(n_i, bofs_i, abeg_i, aend_i, abeg_id_i, aend_id_i,
dummy) = cfg.CreateAccumBlockTransaction(bofs[i])[OFS]
for j in range(n_i):
# only use the first one
TEST_ABMOFS = cfg.CreateChunkHead(bofs_i[j], abeg_i[j],
abeg_id_i[j], aend_id_i[j],
TEST_UMCFG)[0]
ans = cfg.CreateDramReadTransaction(TEST_ABMOFS, TEST_UMCFG, 0)
st.Resize(ans.shape[0])
npd.copyto(i_data[0], TEST_ABMOFS)
npd.copyto(i_data[1], TEST_UMCFG["lmpad"][0])
npd.copyto(i_data[2], TEST_UMCFG["mboundary"][0])
npd.copyto(i_data[3], TEST_UMCFG["mboundary_lmwidth"][0])
i_data[4][0] = TEST_UMCFG["mlinear"][0]
i_data[5][
0] = 1 if TEST_UMCFG["mwrap"][0] == UmiModel.MEM_WRAP else 0
test.Expect(
tuple(ans[k][:, newaxis]
for k in ("cmd_type", "islast", "addr", "ofs", "len")))
yield from master.Send(i_data)
for i in range(100):
yield ck_ev
for i in range(300):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
scb = Scoreboard()
test1 = scb.GetTest("test1")
st = Stacker(N,
callbacks=[
test1.Get,
lambda x: print("Print with name: {}".format(x.o))
])
bg = BusGetter(callbacks=[st.Get])
yield rs_ev
yield ck_ev
master = OneWire.Master(src_val, src_dat, ck_ev, callbacks=[print])
slave = OneWire.Slave(dst_val, dst_dat, ck_ev, callbacks=[print, bg.Get])
values = master.values
arr = np.random.randint(16, size=(N * 3, 2)).astype(np.int32)
golden = np.sum(np.reshape(arr, (-1, 6)),
axis=1,
keepdims=1,
dtype=np.int32)
test1.Expect((golden, )) # must pass
# test1.Expect((golden+1,)) # must fail
ITER = not getenv("ITER") is None
print("Iteration mode is set to {}".format(ITER))
if ITER:
def it():
for i in arr:
print(arr)
print(i)
np.copyto(values.i, i)
yield values
yield from master.SendIter(it())
else:
for i in arr:
np.copyto(values.i, i)
yield from master.Send(values)
for i in range(10):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
# Calculate answer
# See MyModel.py for more information.
coeff_test = M.coeff_test
rgbs = M.RandomPixelStreams()
yuvs = M.Yuv422(M.Rgb2Yuv(rgbs))
gold_rgb = np.hstack(rgbs)
gold_y = np.concatenate([img[0] for img in yuvs])
gold_u = np.concatenate([img[1] for img in yuvs])
gold_v = np.concatenate([img[2] for img in yuvs])
N_Y = gold_y.shape[0]
N_UV = gold_u.shape[0]
# Connect to Verilog
# Connect to the Verilog wire (please see the document)
# TODO
'''from here
to here
'''
# Construct clock and reset event
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
# Mostly you only need to change the size of Stacker
scb = Scoreboard("Rgb888ToYuv422")
testy = scb.GetTest("Y")
testu = scb.GetTest("U")
testv = scb.GetTest("V")
sty = Stacker(N_Y, callbacks=[testy.Get])
stu = Stacker(N_UV, callbacks=[testu.Get])
stv = Stacker(N_UV, callbacks=[testv.Get])
bgy = BusGetter(callbacks=[sty.Get])
bgu = BusGetter(callbacks=[stu.Get])
bgv = BusGetter(callbacks=[stv.Get])
# Construct master (driver) and slave (monitor) and
# connect slave to the scoreboard.
# Choose to use OneWire or TwoWire accordingly.
# TODO
# NOTE: Construct your master with A=1, B=1 to send data in every cycle.
'''
from here
to here
'''
# Extract the data bus of master
# For creating the iterator (see Iter() below) easily.
# TODO
'''
from here
to here
'''
# Write constant value.
# Let enable = 1 for clock gating.
# TODO
'''
from here
to here
'''
# Check the data at slave.
# TODO
'''from here
to here
'''
# start simulation
# Wait 1 extra cycle after reset
yield rst_out_ev
yield ck_ev
# Then send to the DUT.
# NOTE: DO NOT set latency.
# Use an iterator to set the mdata construted above.
'''
from here
to here
'''
# Wait 100 cycles and Finish
for i in range(100):
yield ck_ev
assert sty.is_clean
assert stu.is_clean
assert stv.is_clean
FinishSim()
def main():
# Calculate answer
rgbs = M.RandomPixelStreams()
yuvs = M.Rgb2Yuv(rgbs)
coeff_test = M.coeff_test
gold_in_px = np.hstack(rgbs)
gold_in_coeff = np.vstack(
np.repeat(np.reshape(c[1], (1, -1)), c[0], axis=0) for c in coeff_test)
gold_out = np.hstack(yuvs)
N = gold_out.shape[1]
# Connect to Verilog
(
# pixel, coeff, y, u, v
pvalid,
pready,
cvalid,
cready,
yvalid,
yready,
uvalid,
uready,
vvalid,
vready,
pdata,
cdata,
ydata,
udata,
vdata,
) = CreateBuses([
(("dut", "rgb_valid"), ),
(("dut", "rgb_ready"), ),
(("dut", "coeffs_valid"), ),
(("dut", "coeffs_ready"), ),
(("dut", "y_valid"), ),
(("dut", "y_ready"), ),
(("dut", "u_valid"), ),
(("dut", "u_ready"), ),
(("dut", "v_valid"), ),
(("dut", "v_ready"), ),
(("dut", "rgb_data", (3, )), ),
(("dut", "coeffs_data", (9, )), ),
(("dut", "y_data"), ),
(("dut", "u_data"), ),
(("dut", "v_data"), ),
])
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
scb = Scoreboard("Rgb2Yuv")
testy = scb.GetTest("Y")
testu = scb.GetTest("U")
testv = scb.GetTest("V")
sty = Stacker(N, callbacks=[testy.Get])
stu = Stacker(N, callbacks=[testu.Get])
stv = Stacker(N, callbacks=[testv.Get])
bgy = BusGetter(callbacks=[sty.Get])
bgu = BusGetter(callbacks=[stu.Get])
bgv = BusGetter(callbacks=[stv.Get])
masterc = TwoWire.Master(cvalid, cready, cdata, ck_ev, A=1, B=2)
masterp = TwoWire.Master(pvalid, pready, pdata, ck_ev, A=1, B=2)
slavey = TwoWire.Slave(yvalid,
yready,
ydata,
ck_ev,
A=1,
B=2,
callbacks=[bgy.Get])
slaveu = TwoWire.Slave(uvalid,
uready,
udata,
ck_ev,
A=1,
B=2,
callbacks=[bgu.Get])
slavev = TwoWire.Slave(vvalid,
vready,
vdata,
ck_ev,
A=1,
B=2,
callbacks=[bgv.Get])
mdatac = masterc.values
mdatap = masterp.values
testy.Expect((gold_out[0, :, np.newaxis], ))
testu.Expect((gold_out[1, :, np.newaxis], ))
testv.Expect((gold_out[2, :, np.newaxis], ))
# start simulation
yield rst_out_ev
yield ck_ev
def IterC():
for i in range(N):
np.copyto(mdatac.coeffs_data, gold_in_coeff[i, :])
yield mdatac
def IterP():
for i in range(N):
np.copyto(mdatap.rgb_data, gold_in_px[:, i])
yield mdatap
Fork(masterc.SendIter(IterC()))
yield from masterp.SendIter(IterP())
for i in range(100):
yield ck_ev
assert sty.is_clean
assert stu.is_clean
assert stv.is_clean
FinishSim()
def main():
seed = np.random.randint(10000)
print("Seed for this run is {}".format(seed))
np.random.seed(seed)
N = 250
golden = np.random.randint(100, size=(N, 2))
scb = Scoreboard("Controller")
test = scb.GetTest("Merge")
st = Stacker(N, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
(
srdy0,
sack0,
sdata0,
srdy1,
sack1,
sdata1,
drdy,
dack,
ddata,
) = CreateBuses([
((
"",
"src0_rdy",
), ),
((
"",
"src0_ack",
), ),
((
"",
"src0_data",
), ),
((
"",
"src1_rdy",
), ),
((
"",
"src1_ack",
), ),
((
"",
"src1_data",
), ),
((
"",
"dst_rdy",
), ),
((
"",
"dst_canack",
), ),
(("", "dst_data", (2, )), ),
])
master0 = TwoWire.Master(srdy0, sack0, sdata0, ck_ev, A=1, B=2)
master1 = TwoWire.Master(srdy1, sack1, sdata1, ck_ev, A=1, B=2)
slave = TwoWire.Slave(drdy,
dack,
ddata,
ck_ev,
callbacks=[bg.Get],
A=1,
B=3)
yield rst_out_ev
yield ck_ev
def It(target, it):
for i in it:
target[0][0] = i
yield target
test.Expect((golden, ))
Fork(master0.SendIter(It(sdata0.values, golden[:, 0].flat)))
yield from master1.SendIter(It(sdata1.values, golden[:, 1].flat))
for i in range(10):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
scb = Scoreboard("WriteCollector")
test = scb.GetTest("test")
st = Stacker(callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
master_a = TwoWire.Master(a_rdy_bus, a_ack_bus, a_bus, ck_ev)
master_d = TwoWire.Master(d_rdy_bus, d_ack_bus, d_bus, ck_ev)
slave = TwoWire.Slave(w_rdy_bus,
w_ack_bus,
w_bus,
ck_ev,
callbacks=[bg.Get])
yield rst_out_ev
# global
master_ad = master_a.values
master_dd = master_d.values
# simulation
n_bofs, bofs = conf.CreateBlockTransaction()
for i in range(n_bofs):
(n_o, bofs_o, abeg_o, aend_o, abeg_id_o, aend_id_o,
dummy) = conf.CreateAccumBlockTransaction(bofs[i])[3]
for j in range(n_o):
# Expect?
(n_aofs_o, agofs_o, alofs_o, rt_i_o, rg_li_o,
rg_ri_o) = conf.CreateAccumTransaction(abeg_o[j], aend_o[j])
accum_idx_o, warpid_o, rg_flat_o, rt_flat_o = conf.CreateAccumWarpTransaction(
abeg_o[j], aend_o[j], rt_i_o, rg_li_o, rg_ri_o, conf.n_o)
bgofs_o, blofs_o, valid_o = conf.CreateBofsValidTransaction(
bofs[i], warpid_o)
addr_o = conf.CreateVectorAddressTransaction(
bgofs_o[:, 0, :], agofs_o[accum_idx_o], rg_flat_o,
conf.umcfg_o['mlinear'], conf.umcfg_o, False)
valid_o_packed = npd.bitwise_or.reduce(
valid_o << npi.arange(VSIZE)[newaxis, :], axis=1).astype('u4')
# output part
if addr_o.size:
da, dm = conf.CreateDramWriteTransaction(valid_o, addr_o)
dm_packed = npd.bitwise_or.reduce(
dm << npi.arange(conf.DRAM_ALIGN)[newaxis, :], axis=1)
st.Resize(da.shape[0])
test.Expect((da[:, newaxis], dm_packed[:, newaxis]))
# Send
def iter_a():
for k in range(addr_o.shape[0]):
npd.copyto(master_ad[0], addr_o[k])
master_ad[1][0] = valid_o_packed[k]
yield master_ad
Fork(master_d.SendIter(repeat(tuple(), da.shape[0])))
yield from master_a.SendIter(iter_a())
for i in range(100):
yield ck_ev
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
# Calculate answer
coeff_test = M.coeff_test
rgbs = M.RandomPixelStreams()
yuvs = M.Yuv422(M.Rgb2Yuv(rgbs))
gold_rgb = np.hstack(rgbs)
gold_y = np.concatenate([img[0] for img in yuvs])
gold_u = np.concatenate([img[1] for img in yuvs])
gold_v = np.concatenate([img[2] for img in yuvs])
N_Y = gold_y.shape[0]
N_UV = gold_u.shape[0]
# Connect to Verilog
(
# pixel, number, coeff, y, u, v
pvalid,
pready,
nvalid,
nready,
cvalid,
cready,
yvalid,
yready,
uvalid,
uready,
vvalid,
vready,
pdata,
ndata,
cdata,
ydata,
udata,
vdata,
) = CreateBuses([
(("dut", "rgb_valid"), ),
(("dut", "rgb_ready"), ),
(("dut", "pixel_count_valid"), ),
(("dut", "pixel_count_ready"), ),
(("dut", "coeff_valid"), ),
(("dut", "coeff_ready"), ),
(("dut", "y_valid"), ),
(("dut", "y_ready"), ),
(("dut", "u_valid"), ),
(("dut", "u_ready"), ),
(("dut", "v_valid"), ),
(("dut", "v_ready"), ),
(("dut", "rgb_data", (3, )), ),
(("dut", "pixel_count"), ),
(("dut", "coeff_data"), ),
(("dut", "y_data"), ),
(("dut", "u_data"), ),
(("dut", "v_data"), ),
])
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
scb = Scoreboard("Rgb888ToYuv422")
testy = scb.GetTest("Y")
testu = scb.GetTest("U")
testv = scb.GetTest("V")
sty = Stacker(N_Y, callbacks=[testy.Get])
stu = Stacker(N_UV, callbacks=[testu.Get])
stv = Stacker(N_UV, callbacks=[testv.Get])
bgy = BusGetter(callbacks=[sty.Get])
bgu = BusGetter(callbacks=[stu.Get])
bgv = BusGetter(callbacks=[stv.Get])
masterc = TwoWire.Master(cvalid, cready, cdata, ck_ev)
mastern = TwoWire.Master(nvalid, nready, ndata, ck_ev)
masterp = TwoWire.Master(pvalid, pready, pdata, ck_ev, A=1, B=2)
slavey = TwoWire.Slave(yvalid,
yready,
ydata,
ck_ev,
A=1,
B=2,
callbacks=[bgy.Get])
slaveu = TwoWire.Slave(uvalid,
uready,
udata,
ck_ev,
A=1,
B=2,
callbacks=[bgu.Get])
slavev = TwoWire.Slave(vvalid,
vready,
vdata,
ck_ev,
A=1,
B=2,
callbacks=[bgv.Get])
mdatac = masterc.values
mdatan = mastern.values
mdatap = masterp.values
testy.Expect((gold_y[:, np.newaxis], ))
testu.Expect((gold_u[:, np.newaxis], ))
testv.Expect((gold_v[:, np.newaxis], ))
# start simulation
yield rst_out_ev
yield ck_ev
def IterC():
for i in coeff_test:
for j in i[1].flat:
mdatac.coeff_data[0] = j
yield mdatac
def IterN():
for i in coeff_test:
mdatan.pixel_count[0] = i[0]
yield mdatan
def IterP():
for i in range(N_Y):
np.copyto(mdatap.rgb_data, gold_rgb[:, i])
yield mdatap
th1 = JoinableFork(masterc.SendIter(IterC()))
th2 = JoinableFork(mastern.SendIter(IterN()))
th3 = JoinableFork(masterp.SendIter(IterP()))
yield from th1.Join()
yield from th2.Join()
yield from th3.Join()
th1.Destroy()
th2.Destroy()
th3.Destroy()
for i in range(100):
yield ck_ev
assert sty.is_clean
assert stu.is_clean
assert stv.is_clean
FinishSim()
def main():
seed = np.random.randint(10000)
print("Seed for this run is {}".format(seed))
np.random.seed(seed)
N = 100
indat_val = np.random.randint(256, size=N)
indat_rl = np.random.randint(4, size=N)
golden = np.array(
[vv for v, rl in zip(indat_val, indat_rl) for vv in ToArr(v, rl)],
dtype=np.int32)
scb = Scoreboard("Controller")
test = scb.GetTest("Rld")
st = Stacker(golden.shape[0], callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
(
srdy,
sack,
sdata,
drdy,
dack,
ddata,
) = CreateBuses([
((
"",
"src_rdy",
), ),
((
"",
"src_ack",
), ),
(
("", "src_data"),
("", "src_run_len"),
),
((
"",
"dst_rdy",
), ),
((
"",
"dst_canack",
), ),
((
"",
"dst_data",
), ),
])
master = TwoWire.Master(srdy, sack, sdata, ck_ev, A=1, B=5)
slave = TwoWire.Slave(drdy,
dack,
ddata,
ck_ev,
callbacks=[bg.Get],
A=1,
B=2)
yield rst_out_ev
yield ck_ev
def It():
mv = sdata.values
for v, rl in zip(indat_val, indat_rl):
np.copyto(mv[0], v)
np.copyto(mv[1], rl)
yield mv
test.Expect((golden[:, np.newaxis], ))
yield from master.SendIter(It())
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
# Calculate answer
coeff_test = M.coeff_test
N_ANS = sum(x[0] for x in coeff_test)
ans = np.vstack(
np.repeat(np.reshape(c[1], (1, -1)), c[0], axis=0) for c in coeff_test)
# Connect to Verilog
(pvalid, pready, cvalid, cready, csvalid, csready, pdata, cdata,
csdata) = CreateBuses([
(("dut", "pixel_count_valid"), ),
(("dut", "pixel_count_ready"), ),
(("dut", "coeff_valid"), ),
(("dut", "coeff_ready"), ),
(("dut", "coeffs_valid"), ),
(("dut", "coeffs_ready"), ),
(("dut", "pixel_count"), ),
(("dut", "coeff_data"), ),
(("", "csdata_sext", (9, )), ),
])
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
scb = Scoreboard("CoeffCollect")
test = scb.GetTest("CoeffCollect")
st = Stacker(N_ANS, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
masterp = TwoWire.Master(pvalid, pready, pdata, ck_ev)
masterc = TwoWire.Master(cvalid, cready, cdata, ck_ev)
slave = TwoWire.Slave(csvalid,
csready,
csdata,
ck_ev,
A=1,
B=2,
callbacks=[bg.Get])
mdatap = masterp.values
mdatac = masterc.values
test.Expect((ans, ))
# start simulation
yield rst_out_ev
yield ck_ev
def IterP():
for i in coeff_test:
mdatap.pixel_count[0] = i[0]
yield mdatap
def IterC():
for i in coeff_test:
for j in i[1].flat:
mdatac.coeff_data[0] = j
yield mdatac
th_1 = JoinableFork(masterp.SendIter(IterP()))
th_2 = JoinableFork(masterc.SendIter(IterC()))
yield from th_1.Join()
yield from th_2.Join()
th_1.Destroy()
th_2.Destroy()
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
(("dut", "inst_commit_dval"), ),
])
src_bus, inst_bus = CreateBuses([
(
("dut", "i_bofs", (VDIM, )),
(None, "i_aofs_beg", (VDIM, )),
(None, "i_aofs_end", (VDIM, )),
(None, "i_dual_axis"),
(None, "i_dual_order"),
(None, "i_bgrid_step", (VDIM, )),
(None, "i_bsub_up_order", (VDIM, )),
(None, "i_bsub_lo_order", (VDIM, )),
(None, "i_aboundary", (VDIM, )),
(None, "i_inst_id_begs", (VDIM + 1, )),
(None, "i_inst_id_ends", (VDIM + 1, )),
),
(
("dut", "o_bofs", (VDIM, )),
(None, "o_aofs", (VDIM, )),
(None, "o_pc"),
(None, "o_warpid"),
),
])
scb = Scoreboard("SimdDriver")
tst = scb.GetTest("test", 10)
col = Stacker(callbacks=[tst.Get])
bg = BusGetter(callbacks=[col.Get])
RegisterCoroutines([
main(),
])
try:
from os import environ
ST_MODE = bool(environ["STENCIL"])
except:
ST_MODE = False
assert not ST_MODE, "TODO"
cfg = default_sample_conf
VSIZE = cfg.VSIZE
VDIM = cfg.VDIM
DIM = cfg.DIM
CV_BW = cfg.LG_VSIZE
N_CFG = cfg.n_i0[1][-1]
N_SLUT = 2
scb = Scoreboard("AccumWarpLooper")
tst = scb.GetTest("test")
dc = Stacker(0, callbacks=[tst.Get])
bg = BusGetter(callbacks=[dc.Get])
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
(bofs_rdy, bofs_ack, av_rdy, av_ack) = CreateBuses([
(("bofs_rdy", ), ),
(("bofs_ack", ), ),
(("av_rdy", ), ),
(("av_canack", ), ),
])
bofs_bus, av_bus = CreateBuses([
(
("dut", "i_bofs", (VDIM, )),
(None, "i_abeg", (VDIM, )),
(None, "i_aend", (VDIM, )),
def main():
scb = Scoreboard("AccumBlockLooper")
test_i0 = scb.GetTest("test_i0")
test_i1 = scb.GetTest("test_i1")
test_dma = scb.GetTest("test_dma")
test_o = scb.GetTest("test_o")
test_alu = scb.GetTest("test_alu")
st_i0 = Stacker(0, callbacks=[test_i0.Get])
st_i1 = Stacker(0, callbacks=[test_i1.Get])
st_dma = Stacker(0, callbacks=[test_dma.Get])
st_o = Stacker(0, callbacks=[test_o.Get])
st_alu = Stacker(0, callbacks=[test_alu.Get])
bg_i0 = BusGetter(callbacks=[st_i0.Get])
bg_i1 = BusGetter(callbacks=[st_i1.Get])
bg_dma = BusGetter(callbacks=[st_dma.Get])
bg_o = BusGetter(callbacks=[st_o.Get])
bg_alu = BusGetter(callbacks=[st_alu.Get])
master = TwoWire.Master(s_rdy_bus, s_ack_bus, s_bus, ck_ev)
i_data = master.values
slave_i0 = TwoWire.Slave(i0_rdy_bus,
i0_ack_bus,
i0_bus,
ck_ev,
callbacks=[bg_i0.Get])
slave_i1 = TwoWire.Slave(i1_rdy_bus,
i1_ack_bus,
i1_bus,
ck_ev,
callbacks=[bg_i1.Get])
slave_dma = TwoWire.Slave(dma_rdy_bus,
dma_ack_bus,
dma_bus,
ck_ev,
callbacks=[bg_dma.Get])
slave_o = TwoWire.Slave(o_rdy_bus,
o_ack_bus,
o_bus,
ck_ev,
callbacks=[bg_o.Get])
slave_alu = TwoWire.Slave(alu_rdy_bus,
alu_ack_bus,
alu_bus,
ck_ev,
callbacks=[bg_alu.Get])
yield rst_out_ev
yield ck_ev
n_bofs, bofs, = cfg.CreateBlockTransaction()
ans_i0, ans_i1, ans_dma, ans_o, ans_alu, = cfg.CreateAccumBlockTransaction(
bofs[0])
n_i0, bofs_i0, abeg_i0, aend_i0, abeg_id_i0, aend_id_i0, dummy, = ans_i0
n_i1, bofs_i1, abeg_i1, aend_i1, abeg_id_i1, aend_id_i1, dummy, = ans_i1
n_dma, bofs_dma, abeg_dma, aend_dma, abeg_id_dma, aend_id_dma, which_dma = ans_dma
n_o, bofs_o, abeg_o, aend_o, abeg_id_o, aend_id_o, dummy, = ans_o
n_alu, bofs_alu, abeg_alu, aend_alu, abeg_id_alu, aend_id_alu, dummy, = ans_alu
# start simulation
npd.copyto(i_data[0], bofs[0])
npd.copyto(i_data[1], cfg.acfg['local'][0])
npd.copyto(i_data[2], cfg.acfg['end'][0])
npd.copyto(i_data[3], cfg.acfg['total'][0])
npd.copyto(i_data[4], cfg.n_i0[0])
npd.copyto(i_data[5], cfg.n_i0[1])
npd.copyto(i_data[6], cfg.n_i1[0])
npd.copyto(i_data[7], cfg.n_i1[1])
npd.copyto(i_data[8], cfg.n_o[0])
npd.copyto(i_data[9], cfg.n_o[1])
npd.copyto(i_data[10], cfg.n_inst[0])
npd.copyto(i_data[11], cfg.n_inst[1])
test_i0.Expect(
(bofs_i0, abeg_i0, aend_i0, abeg_id_i0[:,
newaxis], aend_id_i0[:,
newaxis]))
test_i1.Expect(
(bofs_i1, abeg_i1, aend_i1, abeg_id_i1[:,
newaxis], aend_id_i1[:,
newaxis]))
test_dma.Expect((bofs_dma, which_dma[:, newaxis], abeg_dma,
abeg_id_dma[:, newaxis], aend_id_dma[:, newaxis]))
test_o.Expect(
(bofs_o, abeg_o, aend_o, abeg_id_o[:, newaxis], aend_id_o[:, newaxis]))
test_alu.Expect((bofs_alu, abeg_alu, aend_alu))
st_i0.Resize(n_i0)
st_i1.Resize(n_i1)
st_dma.Resize(n_dma)
st_o.Resize(n_o)
st_alu.Resize(n_alu)
yield from master.Send(i_data)
for i in range(300):
yield ck_ev
assert st_i0.is_clean
assert st_i1.is_clean
assert st_dma.is_clean
assert st_o.is_clean
assert st_alu.is_clean
FinishSim()
def main():
seed = np.random.randint(10000)
print("Seed for this run is {}".format(seed))
np.random.seed(seed)
N = 100
golden = np.random.randint(4, size=(N, 2))
scb = Scoreboard("Controller")
test = scb.GetTest("Vec2Arr")
st = Stacker(golden.shape[0], callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
(
srdy,
sack,
sdata,
drdy,
dack,
ddata,
) = CreateBuses([
((
"",
"src_rdy",
), ),
((
"",
"src_ack",
), ),
(("", "src_data"), ),
((
"",
"dst_rdy",
), ),
((
"",
"dst_canack",
), ),
(("", "dst_arr", (2, )), ),
])
master = TwoWire.Master(srdy, sack, sdata, ck_ev, A=1, B=5)
slave = TwoWire.Slave(drdy,
dack,
ddata,
ck_ev,
callbacks=[bg.Get],
A=1,
B=2)
yield rst_out_ev
yield ck_ev
def It():
mv = sdata.values
for i in golden.flat:
np.copyto(mv[0], i)
yield mv
test.Expect((golden, ))
yield from master.SendIter(It())
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
# Calculate answer.
# This creates sorted and non-sorted features (answer and features_np).
features = M.ComputeImages(M.LoadImages())
features_np = np.array(features, dtype=np.int32)
answer = np.array(M.SortFeatures(features), dtype=np.int32)
N_IMG = 16
# Connect to Verilog
# Connect to the Verilog wire (please see the document)
(
ivalid,
ovalid,
idata,
odata,
) = CreateBuses([
(("dut", "img_valid"), ),
(("dut", "o_valid"), ),
(
("dut", "img_tag"),
(None, "img_type"),
(None, "img_num"),
(None, "img_sum"),
),
(
("dut", "o_tag"),
(None, "o_type"),
),
])
# Construct clock and reset event
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
# Mostly you only need to change the size of Stacker
scb = Scoreboard("ISE")
test = scb.GetTest(f"Sorter")
st = Stacker(N_IMG, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
# Construct master (driver) and slave (monitor) and
# connect slave to the scoreboard.
master = OneWire.Master(ivalid, idata, ck_ev)
slave = OneWire.Slave(ovalid, odata, ck_ev, callbacks=[bg.Get])
# Extract the data bus of master
# For creating the iterator (see Iter() below) easily.
mdata = master.values
# Check the data at slave.
# This create a tuple of two column vectors of size 16.
# The first one is o_tag, and the second one is o_type.
test.Expect((answer[:, 1, np.newaxis], answer[:, 0, np.newaxis]))
# Start simulation
# Wait 1 extra cycle after reset
yield rst_out_ev
yield ck_ev
# Then send to the DUT (every 50 cycles).
# Use an iterator to set the mdata construted above.
def Iter():
for i in range(N_IMG):
mdata.img_tag[0] = features_np[i, 4]
mdata.img_type[0] = features_np[i, 0]
mdata.img_num[0] = features_np[i, 2]
mdata.img_sum[0] = features_np[i, 3]
yield mdata
yield from master.SendIter(Iter(), latency=50)
# Wait 100 cycles and Finish
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
def main():
# Calculate answer
# See MyModel.py for more information.
rgbs = M.RandomPixelStreams()
yuvs = M.Rgb2Yuv(rgbs)
coeff_test = M.coeff_test
gold_in_px = np.hstack(rgbs)
gold_in_coeff = np.vstack(
np.repeat(np.reshape(c[1], (1,-1)), c[0], axis=0)
for c in coeff_test
)
gold_out = np.hstack(yuvs)
N = gold_out.shape[1]
# Connect to Verilog
# Connect to the Verilog wire (please see the document)
# TODO
'''from here
to here
'''
# Construct clock and reset event
rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev"])
# Initialization
# Mostly you only need to change the size of Stacker
scb = Scoreboard("Rgb2Yuv")
testy = scb.GetTest("Y")
testu = scb.GetTest("U")
testv = scb.GetTest("V")
sty = Stacker(N, callbacks=[testy.Get])
stu = Stacker(N, callbacks=[testu.Get])
stv = Stacker(N, callbacks=[testv.Get])
bgy = BusGetter(callbacks=[sty.Get])
bgu = BusGetter(callbacks=[stu.Get])
bgv = BusGetter(callbacks=[stv.Get])
# Construct master (driver) and slave (monitor) and
# connect slave to the scoreboard.
# Choose to use OneWire or TwoWire accordingly.
# TODO
# NOTE: Construct your master with A=1, B=1 to send data in every cycle.
# NOTE: Construct your master with A=1, B=1 to send data in every cycle.
'''
from here
to here
'''
# Extract the data bus of master
# For creating the iterator (see Iter() below) easily.
# TODO
'''
from here
to here
'''
# Check the data at slave.
# This create a tuple of 28.
# TODO
'''from here
to here
'''
# start simulation
# Wait 1 extra cycle after reset
yield rst_out_ev
yield ck_ev
# Then send to the DUT.
# NOTE: DO NOT set latency.
# Use an iterator to set the mdata construted above.
'''
from here
to here
'''
# Wait 100 cycles and Finish
for i in range(100):
yield ck_ev
assert sty.is_clean
assert stu.is_clean
assert stv.is_clean
FinishSim()
def main():
seed = np.random.randint(10000)
print("Seed for this run is {}".format(seed))
np.random.seed(seed)
N = 250
golden = np.random.randint(100, size=(N, 2))
scb = Scoreboard("Controller")
PARALLEL_BRD = getenv("IN_ORDER") is None
test0 = scb.GetTest("Broadcast0" if PARALLEL_BRD else "BroadcastInOrder0")
test1 = scb.GetTest("Broadcast1" if PARALLEL_BRD else "BroadcastInOrder1")
st0 = Stacker(N, callbacks=[test0.Get])
st1 = Stacker(N, callbacks=[test1.Get])
bg0 = BusGetter(callbacks=[st0.Get])
bg1 = BusGetter(callbacks=[st1.Get])
(
srdy,
sack,
sdata,
drdy0,
dack0,
ddata0,
drdy1,
dack1,
ddata1,
) = CreateBuses([
((
"",
"src_rdy",
), ),
((
"",
"src_ack",
), ),
(("", "src_data", (2, )), ),
((
"",
"dst0_rdy",
), ),
((
"",
"dst0_canack",
), ),
((
"",
"dst0_data",
), ),
((
"",
"dst1_rdy",
), ),
((
"",
"dst1_canack",
), ),
((
"",
"dst1_data",
), ),
])
cb0 = [bg0.Get]
cb1 = [bg1.Get]
if not PARALLEL_BRD:
class OrderCheck:
def __init__(self):
self.received_diff = 0
def CbAdd(self, x):
self.received_diff += 1
def CbMinus(self, x):
self.received_diff -= 1
assert self.received_diff >= 0
chk = OrderCheck()
cb0.append(chk.CbAdd)
cb1.append(chk.CbMinus)
master = TwoWire.Master(srdy, sack, sdata, ck_ev, A=1, B=2)
slave0 = TwoWire.Slave(drdy0,
dack0,
ddata0,
ck_ev,
callbacks=cb0,
A=3,
B=8)
slave1 = TwoWire.Slave(drdy1,
dack1,
ddata1,
ck_ev,
callbacks=cb1,
A=5,
B=8)
yield rst_out_ev
yield ck_ev
def It():
mv = sdata.values
for i in golden:
np.copyto(mv[0], i)
yield mv
test0.Expect((golden[:, 0, np.newaxis], ))
test1.Expect((golden[:, 1, np.newaxis], ))
yield from master.SendIter(It())
for i in range(10):
yield ck_ev
assert st0.is_clean and st1.is_clean
FinishSim()
