def ram_sim(self):
# Simulate a ram full of constants
yield Passive()
while True:
addr = yield self.bf.ram.addr
yield self.bf.ram.data.eq(addr * 0x10)
yield
def buf_sim(self):
yield Passive()
while True:
addr = yield self.read.addr
for i in range(3):
yield self.read.data[i].eq(self.data_words[i][addr % 8])
yield
def note_sink():
NoteMsg = namedtuple('NoteMsg', 'onoff channel note velocity')
expected = [
NoteMsg(True, 3, 60, 64),
NoteMsg(True, 3, 67, 96),
NoteMsg(False, 3, 60, 32),
NoteMsg(False, 3, 67, 0),
]
expected_index = 0
yield Passive()
#280
yield i_note_ready.eq(False)
while True:
valid = yield design.note_msg_out.o_valid
#280
ready = yield i_note_ready
if valid and not ready:
yield from delay(expected_index)
#280
yield i_note_ready.eq(True)
elif valid and ready:
#280
yield i_note_ready.eq(False)
actual = NoteMsg(
(yield design.note_msg_out.o_data.onoff),
(yield design.note_msg_out.o_data.channel),
(yield design.note_msg_out.o_data.note),
(yield design.note_msg_out.o_data.velocity),
)
assert expected_index < len(expected)
assert actual == expected[expected_index], (
f'expected {expected[expected_index]}, got {actual}'
)
expected_index += 1
yield
def tick_proc():
yield Passive()
while True:
yield design.pulse_out.i_ready.eq(True)
yield design.saw_out.i_ready.eq(True)
for i in range(cfg.osc_divisor):
yield
if (yield design.pulse_out.o_valid):
yield design.pulse_out.i_ready.eq(False)
if (yield design.saw_out.o_valid):
yield design.saw_out.i_ready.eq(False)
def rng_process(self):
yield Passive()
# Set new data whenever enable is set
for word in flatten_list(self.rng_data):
yield self.lw.rng_in.eq(word)
yield
while not (yield self.lw.rng_enable):
yield
yield # Allow one more enable
# That's all the data we have
while not (yield self.lw.rng_enable):
yield
fail("Requested more random numbers than expected")
def sample_out_process():
def recv_sample():
#280 yield design.samples_out.i_ready.eq(True)
yield i_ready.eq(True)
for i in range(N + 2):
yield
if (yield design.samples_out.o_valid):
break
#280 yield design.samples_out.i_ready.eq(False)
yield i_ready.eq(False)
yield Passive()
while True:
yield from recv_sample()
yield from delay(M)
def double_buffer(self):
yield Passive()
d = self.data[:]
while True:
yield self.shifter.r_last.eq(0)
for _ in range(self.num_words):
while not (yield self.shifter.r_next):
yield
yield # One extra cycle wait while LFSR updates and memory read occurs
yield self.shifter.r_data.eq(d.pop(0))
yield
while not (yield self.shifter.r_next):
yield
yield self.shifter.r_data.eq(0)
yield self.shifter.r_last.eq(1)
yield
def buf_recorder(self):
# Record LifeDataBuffer writes
yield Passive()
while True:
next = yield self.write.next
addr = yield self.write.addr
data = yield self.write.data
en = yield self.write.en
save = yield self.write.save
rec = self.buf_record
curr_data = rec.written_data[-1] if rec.written_data else None
if next:
rec.written_data.append([-1, -1, -1, -1])
if en:
rec.write_count += 1
curr_data[addr] = data
if save:
rec.saved[addr] = data
yield
def loopback_proc():
yield Passive()
while True:
yield uart.rx_i.eq((yield uart.tx_o))
yield
def TEST_MEM():
yield Passive()
# yield Tick()
# yield Settle()
p = .4 # .5 # probability of mem access in current cycle
from enum import Enum
class MemState(Enum):
FREE = 0
BUSY_READ = 1
BUSY_WRITE = 2
# TODO legacy - not used for now.
# cursed - if we use state == MemState.FREE instead of list, 'timeout_range' generator wouldn't work.
# param need to be passed by reference not by value, for actual binding to be visible in each loop iter.
state = [MemState.FREE]
arbiter = cpu.arbiter
while (True): # that's ok, I'm passive.
import numpy.random as random
rdy = random.choice((0, 1), p=[1 - p, p])
ctr = yield cpu.DEBUG_CTR
if state[0] == MemState.FREE:
ack = yield arbiter.bus.ack
if ack:
yield arbiter.bus.ack.eq(0)
# print(f"DEBUG_CTR: {ctr}, state: {state[0]}")
yield
continue
cyc = yield arbiter.bus.cyc
we = yield arbiter.bus.we
write = cyc and we
read = cyc and not we
mem_addr = yield arbiter.bus.adr
if read and write:
raise ValueError(
"ERROR (TODO handle): simultaneous 'read' and 'write' detected."
)
if read:
state[0] = MemState.BUSY_READ
elif write:
state[0] = MemState.BUSY_WRITE
data = yield arbiter.bus.dat_w
else:
if rdy: # random indicated transaction done in current cycle
yield arbiter.bus.ack.eq(1)
sel = yield arbiter.bus.sel
sel = format(sel, '04b') # '1111' string for full mask
f = lambda x: 0xFF if int(x) == 1 else 0x00
g = lambda val, el: (val << 8) + el
from functools import reduce
mask = reduce(g, map(f, sel))
read_val = 0x0 if mem_addr not in mem_dict else mem_dict[
mem_addr]
if state[0] == MemState.BUSY_WRITE:
mem_dict[mem_addr] = (read_val & ~mask) | (data & mask)
elif state[0] == MemState.BUSY_READ:
read_val &= mask
yield arbiter.bus.dat_r.eq(read_val)
# print(f"cyc {ctr}: fetched {read_val} (from {mem_dict})...")
state[0] = MemState.FREE
yield