def process(): # This design consist purely of combinational logic # so we just loop through all possible input values for i in range(256): yield m.data.eq(i) yield Delay(1e-6) yield Settle()
def TEST_REG(timeout=25 + timeout_cycles):
yield Active()
yield Tick()
yield Settle()
for _ in range(timeout):
en = yield cpu.reg_write_port.en
if en == 1:
addr = yield cpu.reg_write_port.addr
if addr == reg_num:
val = yield cpu.reg_write_port.data
if check_reg and (val != expected_val):
# TODO that mechanism for now allows for only one write to reg, extend it if neccessary.
print(
f"== ERROR: Expected data write to reg x{addr} of value {expected_val},"
f" got value {val}.. \n== fail test: {name}\n")
print(
f"{format(expected_val, '32b')} vs {format(val, '32b')}"
)
exit(1)
return
yield Tick()
if check_reg:
print(
f"== ERROR: Test timeouted! No register write observed. Test: {name}\n"
)
exit(1)
def process():
# Stochastic testing
for _ in range(300):
yield from verify(random.randint(0, 255), random.randint(0, 1),
random.randint(0, 31), random.randint(0, 1),
random.randint(0, 255), random.randint(0, 255),
random.randint(0, 31), random.randint(1, 2))
yield Delay(1e-6)
yield Settle()
def process():
# enable necessary signals for write
for en in range(4):
yield sram.bus.sel[en].eq(1)
yield sram.bus.we.eq(1)
yield sram.bus.cyc.eq(1)
yield sram.bus.stb.eq(1)
# put data and address on bus
yield sram.bus.adr.eq(0x4)
yield sram.bus.dat_w.eq(0xdeadbeef)
yield
# set necessary signal to read bus
# at address 0
yield sram.bus.we.eq(0)
yield sram.bus.adr.eq(0)
yield sram.bus.cyc.eq(1)
yield sram.bus.stb.eq(1)
yield
# see sync_behaviors.py
# for why we need Settle()
yield Settle()
yield from print_sig(sram.bus.adr)
yield from print_sig(sram.bus.dat_r, "h")
# set necessary signal to read bus
# at address 4
yield sram.bus.we.eq(0)
yield sram.bus.adr.eq(0x4)
yield sram.bus.cyc.eq(1)
yield sram.bus.stb.eq(1)
yield
yield Settle()
yield from print_sig(sram.bus.adr)
yield from print_sig(sram.bus.dat_r, "h")
# disable signals
yield sram.bus.cyc.eq(0)
yield sram.bus.stb.eq(0)
yield
def peekmem():
for slot in range(4):
#set address
yield rp.addr.eq(slot)
yield check.check_in.eq(slot)
yield
yield Settle()
print(f"ADDR = {(yield rp.addr)}")
#print data
print(f"mem[{slot}] = {(yield rp.data)}")
def process():
# 18 bits in, 16 bits out
in_bits = [1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1]
expected = [1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0]
def to_num(a):
return sum(b << i for i, b in enumerate(a))
yield e.input.eq(to_num(in_bits))
yield Settle()
self.assertEqual(to_num(expected), (yield e.output))
def process():
# Stochastic testing, currently doesnt work for when it is shifted by 1 symbol
#yield from verify(random.randint(0, 255), random.randint(0, 1), random.randint(0, 31), random.randint(0, 1),
#random.randint(0, 255), random.randint(0, 255), random.randint(0, 31), random.randint(1, 2), random.randint(0, 1), 1, 1)
#yield from verify(random.randint(0, 255), random.randint(0, 1), random.randint(0, 31), random.randint(0, 1),
#random.randint(0, 255), random.randint(0, 255), random.randint(0, 31), random.randint(1, 2), random.randint(0, 1), 1, 1)
for _ in range(300):
yield from verify(random.randint(0, 255), random.randint(0, 1),
random.randint(0, 31), random.randint(0, 1),
random.randint(0, 255), random.randint(0, 255),
random.randint(0, 31), random.randint(1, 2),
random.randint(0, 1), 0, 0)
yield Delay(1e-6)
yield Settle()
def process():
val = 2
yield simple.simple_in.eq(val)
yield
# this will print simple_out = 0 which is the
# reset value even though
# during this cycle, simple_out = 2
# This is because as far as the simulator is concerned
# we can't see changes until the edge right
# before the next clock cycle
print(f"simple_out = {(yield simple.simple_out)}")
val = 3
yield simple.simple_in.eq(val)
yield
yield Settle()
# this will print out 3 as expected becuase
# we use Settle() to advance right to the edge
# before the next clock cycle
print(f"simple_out = {(yield simple.simple_out)}")
def process():
for i in range(512):
yield calc.input.eq(i)
yield Settle()
expected = life_cell(to_bit_list(i, width=9))
self.assertEqual((yield calc.output), expected)
def process():
for ci, val in zip(c.input, inputs):
yield ci.eq(val)
yield Settle()
actual = yield c.output
self.assertEqual(to_bit_list(actual), expected)
def process():
expected = [0, 1, 1, 1, 1, 0, 0, 0]
for i, o in enumerate(expected):
yield e.input.eq(i)
yield Settle()
self.assertEqual(o, (yield e.output))