def elaborate(self, platform):
m = nm.Module()
tx_div = nm.Signal(range(self.divider))
tx_reg = nm.Signal(self.n + 2, reset=1)
tx_cnt = nm.Signal(range(self.n + 3))
m.d.comb += self.tx_o.eq(tx_reg[0])
with m.If(tx_cnt == 0):
# Idle
with m.If(self.valid):
m.d.sync += [
tx_reg.eq(nm.Cat(0, self.data, 1)),
tx_cnt.eq(self.n + 2),
tx_div.eq(self.divider - 1),
]
with m.Else():
# Transmitting
with m.If(tx_div != 0):
# Wait for clock divider
m.d.sync += tx_div.eq(tx_div - 1)
with m.Else():
# Update output state
m.d.sync += [
tx_reg.eq(nm.Cat(tx_reg[1:], 1)),
tx_cnt.eq(tx_cnt - 1),
tx_div.eq(self.divider - 1),
]
return m
def elaborate(self, platform):
m = nm.Module()
cd_sync = nm.ClockDomain("sync")
m.domains += cd_sync
clk100 = platform.request("clk100")
cd_fast = nm.ClockDomain("fast")
m.domains += cd_fast
m.d.comb += cd_fast.clk.eq(clk100.i)
m.submodules.pll = nm.Instance("SB_PLL40_CORE",
p_FEEDBACK_PATH="SIMPLE",
p_DIVR=3,
p_DIVF=40,
p_DIVQ=6,
p_FILTER_RANGE=2,
i_RESETB=1,
i_BYPASS=0,
i_REFERENCECLK=clk100.i,
o_PLLOUTCORE=cd_sync.clk)
reg = 2
cpu_inst = m.submodules.cpu = cpu.CPU(debug_reg=reg)
link_reg = 5
program = [
encoding.IType.encode(1, reg, encoding.IntRegImmFunct.ADDI, reg,
encoding.Opcode.OP_IMM),
# jump back to the previous instruction for infinite loop
encoding.JType.encode(0x1ffffc, link_reg)
]
imem = nm.Memory(width=32, depth=256, init=program)
imem_rp = m.submodules.imem_rp = imem.read_port()
m.d.comb += [
imem_rp.addr.eq(cpu_inst.imem_addr),
cpu_inst.imem_data.eq(imem_rp.data),
]
dmem = nm.Memory(width=32, depth=256)
dmem_rp = m.submodules.dmem_rp = dmem.read_port(transparent=False,
domain="fast")
dmem_wp = m.submodules.dmem_wp = dmem.write_port(domain="fast")
m.d.comb += [
dmem_rp.addr.eq(cpu_inst.dmem_r_addr),
cpu_inst.dmem_r_data.eq(dmem_rp.data),
dmem_wp.addr.eq(cpu_inst.dmem_w_addr),
dmem_wp.data.eq(cpu_inst.dmem_w_data),
]
colours = ["b", "g", "o", "r"]
leds = nm.Cat(platform.request(f"led_{c}") for c in colours)
m.d.sync += leds.eq(cpu_inst.debug_out[13:17])
return m
def sext(immediate, desired_length=32):
"""
Sign extension
Args:
immediate (nm.Value): the immediate to be sign extended
desired_length (int): the desired length of the extended output
Returns:
nm.hdl.ast.Cat: the sign-extended immediate
"""
return nm.Cat(immediate,
nm.Repl(immediate[-1], desired_length - len(immediate)))
def immediate(self):
"""
Construct the sign-extended immediate from the instruction
Returns:
nm.hdl.ast.Cat: the decoded immediate
"""
sorted_imm_fields = sorted(self.IMM_FIELDS,
key=lambda field: field.offset_start)
to_unshuffle = [
self.instr[field.instr_start:field.instr_end]
for field in sorted_imm_fields
]
unshuffled = nm.Cat(0, *to_unshuffle)
return sext(unshuffled)