def elaborate(self, platform):
m = nm.Module()
# Use OSCG so we can still clock with PHYs in reset
# (otherwise, the PHYs stop running the XO).
m.domains.sync = cd_osc = nm.ClockDomain("sync")
m.submodules.oscg = nm.Instance("OSCG", p_DIV=12, o_OSC=cd_osc.clk)
# Hold PHYs in reset
m.d.comb += platform.request("eth_common").rst.eq(1)
# Hold SDRAM in WE to prevent it driving DQ and leave clock low.
sdram = platform.request("sdram")
m.d.comb += sdram.we.eq(1), sdram.clk.eq(0)
# Flash LED
led = platform.request("led")
ctr = nm.Signal(22)
m.d.sync += ctr.eq(ctr + 1)
m.d.comb += led.o.eq(ctr[-1])
# UART on unknown outputs
v = nm.Signal()
p = nm.Signal()
m.d.sync += p.eq(ctr[-4]), v.eq(p != ctr[-4])
for idx, pin in enumerate(platform.outputs):
print(f"{idx:02X} {pin}")
uart = UART(idx)
m.submodules += uart
pin = platform.request(pin)
m.d.comb += pin.o.eq(uart.tx_o), uart.valid.eq(v)
return m
def __init__(self, data, divider=217, n=8):
assert divider >= 1
self.valid = nm.Signal()
self.tx_o = nm.Signal()
self.data = nm.Const(data, n)
self.divider = divider
self.n = n
def elaborate(self, platform):
m = nm.Module()
clk_freq = platform.default_clk_frequency
speed = int(clk_freq // (1 << 4))
frame_counter = nm.Signal(range(speed), reset=speed - 1)
stepctr = nm.Signal(4)
step = nm.Signal(3)
matrix = m.submodules.matrix = LEDMatrix(4, 8, clk_freq)
with m.If(stepctr >= 8):
m.d.comb += step.eq(7 - stepctr[0:3])
with m.Else():
m.d.comb += step.eq(stepctr)
m.d.comb += [
matrix.columns[0].eq(1 << step),
matrix.columns[1].eq(1 << step | 2 << step),
matrix.columns[2].eq(~0 ^ 4 << step),
matrix.columns[3].eq(~0 ^ (1 << step | 8 << step)),
]
with m.If(frame_counter == 0):
m.d.sync += [
stepctr.eq(stepctr + 1),
frame_counter.eq(frame_counter.reset)
]
with m.Else():
m.d.sync += [frame_counter.eq(frame_counter - 1)]
return m
def elaborate(self, platform):
m = nm.Module()
tx_div = nm.Signal(range(self.divider))
tx_reg = nm.Signal(self.n + 2, reset=1)
tx_cnt = nm.Signal(range(self.n + 3))
m.d.comb += self.tx_o.eq(tx_reg[0])
with m.If(tx_cnt == 0):
# Idle
with m.If(self.valid):
m.d.sync += [
tx_reg.eq(nm.Cat(0, self.data, 1)),
tx_cnt.eq(self.n + 2),
tx_div.eq(self.divider - 1),
]
with m.Else():
# Transmitting
with m.If(tx_div != 0):
# Wait for clock divider
m.d.sync += tx_div.eq(tx_div - 1)
with m.Else():
# Update output state
m.d.sync += [
tx_reg.eq(nm.Cat(tx_reg[1:], 1)),
tx_cnt.eq(tx_cnt - 1),
tx_div.eq(self.divider - 1),
]
return m
def __init__(self, width):
"""
Initialiser
Args:
width (int): data width
"""
self.op = nm.Signal()
self.a = nm.Signal(width)
self.b = nm.Signal(width)
self.o = nm.Signal(width)
def __init__(self, num_registers=32):
self.instr_width = 32
self.instr = nm.Signal(self.instr_width)
self.pc_load = nm.Signal()
self.alu_op = nm.Signal()
self.alu_imm = nm.Signal(self.instr_width)
self.rf_write_enable = nm.Signal()
self.rf_write_select = nm.Signal(range(num_registers))
self.rf_read_select_1 = nm.Signal(range(num_registers))
self.rf_read_select_2 = nm.Signal(range(num_registers))
self.rd_mux_op = nm.Signal()
self.alu_mux_op = nm.Signal()
def __init__(self, debug_reg=2):
self.imem_addr = nm.Signal(32)
self.imem_data = nm.Signal(32)
self.dmem_r_addr = nm.Signal(32)
self.dmem_r_data = nm.Signal(32)
self.dmem_w_addr = nm.Signal(32)
self.dmem_w_data = nm.Signal(32)
self.debug_reg = debug_reg
self.debug_out = nm.Signal(32)
def __init__(self, num_registers=32, register_width=32, debug_reg=2):
self.num_registers = num_registers
self.register_width = register_width
self.read_select_1 = nm.Signal(range(self.num_registers))
self.read_select_2 = nm.Signal(range(self.num_registers))
self.read_data_1 = nm.Signal(self.register_width)
self.read_data_2 = nm.Signal(self.register_width)
self.write_enable = nm.Signal()
self.write_select = nm.Signal(self.register_width)
self.write_data = nm.Signal(self.register_width)
self.debug_out = nm.Signal(self.register_width)
self.debug_reg = debug_reg
def __init__(self):
# Inputs
self.byte_address = nm.Signal(32)
self.address_mode = nm.Signal(AddressMode)
self.signed = nm.Signal()
self.dmem_r_data = nm.Signal(32)
# Outputs
self.dmem_r_addr = nm.Signal(30)
self.load_value = nm.Signal(32)
def elaborate(self, platform):
m = nm.Module()
matrix = platform.request("led_matrix", 0)
cols = matrix.columns
rows = matrix.rows
row_idx = nm.Signal(range(len(rows)))
m.d.comb += [
cols.eq(self.columns[row_idx]),
rows.eq(1 << row_idx),
]
with m.If(self.row_counter == 0):
m.d.sync += [
self.row_counter.eq(self.row_counter.reset),
row_idx.eq(row_idx + 1),
]
with m.Else():
m.d.sync += [self.row_counter.eq(self.row_counter - 1)]
return m
def __init__(self):
self.input = nm.Signal()
self.output = nm.Signal()
def __init__(self, num_registers=32):
self.instr_width = 32
self.instr = nm.Signal(self.instr_width)
self.pc_load = nm.Signal()
self.alu_op = nm.Signal()
self.alu_imm = nm.Signal(self.instr_width)
self.rf_write_enable = nm.Signal()
self.rf_write_select = nm.Signal(range(num_registers))
self.rf_read_select_1 = nm.Signal(range(num_registers))
self.rf_read_select_2 = nm.Signal(range(num_registers))
self.rd_mux_op = nm.Signal(RdValue)
self.alu_mux_op = nm.Signal(ALUInput)
self.dmem_address_mode = nm.Signal(data_memory.AddressMode)
self.dmem_signed = nm.Signal()
def __init__(self, rows, cols, sys_clk_freq):
scan_speed = int(sys_clk_freq) >> 8
self.row_counter = nm.Signal(range(scan_speed), reset=scan_speed - 1)
self.columns = nm.Array([nm.Signal(cols) for _ in range(rows)])
def __init__(self, width=32):
self.load = nm.Signal()
self.input_address = nm.Signal(width)
self.pc = nm.Signal(width)
self.pc_next = nm.Signal(width)
self.pc_inc = nm.Signal(width)