def elaborate(self, platform): m = Module() # Create our clock domains. m.domains.fast = self.fast = ClockDomain() m.domains.sync = self.sync = ClockDomain() m.domains.ulpi = self.ulpi = ClockDomain() # Call the hook that will create any submodules necessary for all clocks. self.create_submodules(m, platform) # Generate and connect up our clocks. m.d.comb += [ self.clk_ulpi.eq(self.generate_ulpi_clock(m, platform)), self.clk_sync.eq(self.generate_sync_clock(m, platform)), self.clk_fast.eq(self.generate_fast_clock(m, platform)), ClockSignal(domain="fast").eq(self.clk_fast), ClockSignal(domain="sync").eq(self.clk_sync), ClockSignal(domain="ulpi").eq(self.clk_ulpi), ] # Call the hook that will connect up our reset signals. self.create_ulpi_reset(m, platform) return m
def formal(cls) -> Tuple[Module, List[Signal]]: m = Module() ph = ClockDomain("ph") clk = ClockSignal("ph") m.domains += ph m.d.sync += clk.eq(~clk) s = IC_7416374(clk="ph") m.submodules += s with m.If(s.n_oe): m.d.comb += Assert(s.q == 0) with m.If(~s.n_oe & Rose(clk)): m.d.comb += Assert(s.q == Past(s.d)) with m.If(~s.n_oe & Fell(clk) & ~Past(s.n_oe)): m.d.comb += Assert(s.q == Past(s.q)) sync_clk = ClockSignal("sync") sync_rst = ResetSignal("sync") # Make sure the clock is clocking m.d.comb += Assume(sync_clk == ~Past(sync_clk)) # Don't want to test what happens when we reset. m.d.comb += Assume(~sync_rst) m.d.comb += Assume(~ResetSignal("ph")) return m, [sync_clk, sync_rst, s.n_oe, s.q, s.d]
def elaborate(self, platform): # For virtual platforms just use a regular counter if platform is None: m = Module() counter = Signal(2) domain = getattr(m.d, self.indomain) domain += counter.eq(counter + 1) m.domains += ClockDomain(self.outdomain, reset_less=True) m.d.comb += ClockSignal(self.outdomain).eq(counter[1]) return m m = Module() clkin = Signal() # Buffered output of input clock, into PLL clkfbout = Signal() # Unbuffered feedback out of PLL clkfbout_buf = Signal() # Buffered feedback into PLL clkout = Signal() # Unbuffered output from PLL div4clk = Signal() # Buffered output of output clock m.submodules.clockdiv = Instance("PLLE2_ADV", p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="ZHOLD", p_STARTUP_WAIT="FALSE", p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=4, p_CLKFBOUT_PHASE=0.000, p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.000, p_CLKOUT0_DUTY_CYCLE=0.500, p_CLKIN1_PERIOD=4.000, o_CLKFBOUT=clkfbout, o_CLKOUT0=clkout, i_CLKFBIN=clkfbout_buf, i_CLKIN1=clkin, i_CLKIN2=0, i_CLKINSEL=1, i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_PWRDWN=0, i_RST=0) m.submodules.inbuf = Instance("BUFG", i_I=ClockSignal(self.indomain), o_O=clkin) m.submodules.outbuf = Instance("BUFG", i_I=clkout, o_O=div4clk) m.submodules.clockfb = Instance("BUFG", i_I=clkfbout, o_O=clkfbout_buf) m.domains += ClockDomain(self.outdomain, reset_less=True) m.d.comb += ClockSignal(self.outdomain).eq(div4clk) return m
def elaborate(self, platform): m = Module() locked = Signal() # Create our domains... m.domains.sync = ClockDomain() m.domains.usb = ClockDomain() m.domains.usb_io = ClockDomain() m.domains.fast = ClockDomain() # ... create our 48 MHz IO and 12 MHz USB clock... clk48 = Signal() clk12 = Signal() m.submodules.pll = Instance("SB_PLL40_2F_CORE", i_REFERENCECLK = platform.request(platform.default_clk), i_RESETB = Const(1), i_BYPASS = Const(0), o_PLLOUTCOREA = clk48, o_PLLOUTCOREB = clk12, o_LOCK = locked, # Create a 48 MHz PLL clock... p_FEEDBACK_PATH = "SIMPLE", p_PLLOUT_SELECT_PORTA = "GENCLK", p_PLLOUT_SELECT_PORTB = "SHIFTREG_0deg", p_DIVR = 0, p_DIVF = 47, p_DIVQ = 4, p_FILTER_RANGE = 1, ) # ... and constrain them to their new frequencies. platform.add_clock_constraint(clk48, 48e6) platform.add_clock_constraint(clk12, 12e6) # We'll use our 48MHz clock for everything _except_ the usb domain... m.d.comb += [ ClockSignal("usb") .eq(clk12), ClockSignal("sync") .eq(clk48), ClockSignal("usb_io") .eq(clk48), ClockSignal("fast") .eq(clk48), ResetSignal("usb") .eq(~locked), ResetSignal("sync") .eq(~locked), ResetSignal("usb_io") .eq(~locked), ResetSignal("fast") .eq(~locked) ] return m
def elaborate(self, platform): m = Module() import os dir_path = os.path.dirname(os.path.realpath(__file__)) with open(dir_path + "/sdram_controller.v") as f: platform.add_file("sdram_controller.v", f.read()) dir_dict = { "a": "-", "ba": "-", "cke": "-", "clk": "-", "clk_en": "-", "dq": "-", "dqm": "-", "cas": "-", "cs": "-", "ras": "-", "we": "-", } sdram = platform.request("sdram", dir=dir_dict) m.submodules += Instance( "sdram_controller", i_CLOCK_50=ClockSignal("compute"), i_CLOCK_100=ClockSignal("sdram"), i_CLOCK_100_del_3ns=ClockSignal("sdram_180_deg"), i_rst=ResetSignal("sdram"), i_address=self.address, i_req_read=self.req_read, i_req_write=self.req_write, i_data_in=self.data_in, o_data_out=self.data_out, o_data_valid=self.data_valid, o_write_complete=self.write_complete, o_DRAM_ADDR=sdram.a, o_DRAM_BA=sdram.ba, o_DRAM_CKE=sdram.clk_en, o_DRAM_CLK=sdram.clk, io_DRAM_DQ=sdram.dq, o_DRAM_DQM=sdram.dqm, o_DRAM_CAS_N=sdram.cas, o_DRAM_CS_N=sdram.cs, o_DRAM_RAS_N=sdram.ras, o_DRAM_WE_N=sdram.we) return m
def elaborate(self, platform): m = Module() m.submodules.clock = self._clock m.submodules.efb = self.efb m.domains += ClockDomain("sync") m.d.comb += ClockSignal("sync").eq(self._clock.out) return m
def elaborate(self, platform): m = Module() # Create our domains... m.domains.sync = ClockDomain() m.domains.usb = ClockDomain() m.domains.usb_io = ClockDomain() m.domains.fast = ClockDomain() # ... ensure our clock is never instantiated with a Global buffer. platform.lookup(platform.default_clk).attrs['GLOBAL'] = False # ... create our 48 MHz IO and 12 MHz USB clocks... clk48 = Signal() clk12 = Signal() m.submodules.pll = Instance( "SB_PLL40_2F_PAD", i_PACKAGEPIN=platform.request(platform.default_clk, dir="i"), i_RESETB=Const(1), i_BYPASS=Const(0), o_PLLOUTGLOBALA=clk48, o_PLLOUTGLOBALB=clk12, # Create a 48 MHz PLL clock... p_FEEDBACK_PATH="SIMPLE", p_PLLOUT_SELECT_PORTA="GENCLK", p_PLLOUT_SELECT_PORTB="SHIFTREG_0deg", p_DIVR=0, p_DIVF=63, p_DIVQ=4, p_FILTER_RANGE=1, ) # ... and constrain them to their new frequencies. platform.add_clock_constraint(clk48, 48e6) platform.add_clock_constraint(clk12, 12e6) # We'll use our 48MHz clock for everything _except_ the usb domain... m.d.comb += [ ClockSignal("usb_io").eq(clk48), ClockSignal("fast").eq(clk48), ClockSignal("sync").eq(clk48), ClockSignal("usb").eq(clk12) ] return m
def elaborate(self, platform): m = Module() oserdes = m.submodules.oserdes = Oserdes(data_width=self.bit_width, tristate_width=1, data_rate_oq="ddr", serdes_mode="master", data_rate_tq="buf") m.d.comb += oserdes.oce.eq(1) m.d.comb += oserdes.clk.eq(ClockSignal(self.x4_clockdomain)) m.d.comb += oserdes.clkdiv.eq(ClockSignal()) m.d.comb += oserdes.rst.eq(ResetSignal()) m.d.comb += Cat(oserdes.d[i] for i in reversed(range(1, 9))).eq( self.value) # reversed is needed!!1 m.d.comb += self.pad.eq(oserdes.oq) return m
def elaborate(self, platform): m = Module() # pins ft_clkout_i = platform.request("ft_clkout_i") ft_wr_n_o = platform.request("ft_wr_n_o") ft_txe_n_i = platform.request("ft_txe_n_i") ft_suspend_n_i = platform.request("ft_suspend_n_i") ft_oe_n_o = platform.request("ft_oe_n_o") ft_rd_n_o = platform.request("ft_rd_n_o") ft_siwua_n_o = platform.request("ft_siwua_n_o") ft_data_io = platform.request("ft_data_io") ext1 = platform.request("ext1") pa_en_n_o = platform.request("pa_en_n_o") # clock domains m.domains += ClockDomain("clk60") m.d.comb += ClockSignal("clk60").eq(ft_clkout_i.i) # signals ctr = Signal(8, reset=0) ctr_last = Signal(8, reset=0) ft_txe_last = Signal(1, reset=0) # submodules m.submodules.fifo = fifo = AsyncFIFO(width=8, depth=1024, r_domain="clk60", w_domain="sync") # logic m.d.comb += [ ft_oe_n_o.o.eq(1), ft_rd_n_o.o.eq(1), ft_siwua_n_o.o.eq(1), ft_data_io.oe.eq(1), pa_en_n_o.o.eq(1), ] m.d.comb += [ ft_data_io.o.eq(fifo.r_data), fifo.w_data.eq(ctr), ] with m.If(fifo.w_rdy): m.d.comb += fifo.w_en.eq(1) m.d.sync += ctr.eq(ctr + 1) with m.Else(): m.d.comb += fifo.w_en.eq(0) with m.If(~ft_txe_n_i & ft_suspend_n_i & fifo.r_rdy): m.d.comb += ft_wr_n_o.o.eq(0) m.d.clk60 += fifo.r_en.eq(1) with m.Else(): m.d.comb += ft_wr_n_o.o.eq(1) m.d.clk60 += fifo.r_en.eq(0) return m
def elaborate(self, platform): m = Module() idelay_ctl = m.submodules.idelay_ctl = _IDelayCtrl() m.d.comb += self.ready.eq(idelay_ctl.rdy) m.d.comb += idelay_ctl.refclk.eq(ClockSignal(self.refclk_domain)) m.d.comb += idelay_ctl.rst.eq(ResetSignal(self.refclk_domain)) return m
def elaborate(self, platform): m = Module() # Get the SDRAM pins dir_dict = { "a": "-", "ba": "-", "cke": "-", "clk": "-", "clk_en": "-", "dq": "-", "dqm": "-", "cas": "-", "cs": "-", "ras": "-", "we": "-", } sdram = platform.request("sdram", dir=dir_dict) # Create the controller m.submodules.ctrl = ctrl = Sdram() m.d.comb += [ # Set the chip output pins sdram.a.eq(ctrl.sd_addr), sdram.dqm.eq(ctrl.sd_dqm), sdram.ba.eq(ctrl.sd_ba), sdram.cs.eq(ctrl.sd_cs), sdram.we.eq(ctrl.sd_we), sdram.ras.eq(ctrl.sd_ras), sdram.cas.eq(ctrl.sd_cas), sdram.clk_en.eq(1), sdram.clk.eq(ClockSignal("sdram_clk")), # Set the controller input pins ctrl.init.eq(self.init), ctrl.din.eq(self.data_in), ctrl.addr.eq(self.address), ctrl.we.eq(self.req_write), ctrl.oe.eq(self.req_read), ctrl.sync.eq(self.sync), ctrl.ds.eq(C(0b11, 2)), # Set output pins self.data_out.eq(ctrl.dout) ] # Set dq to input or output depending on sd_data_dir for i in range(16): dq_io = Instance("BB", io_B=sdram.dq[i], i_T=~ctrl.sd_data_dir, i_I=ctrl.sd_data_out[i], o_O=ctrl.sd_data_in[i]) m.submodules += dq_io return m
def elaborate(self, platform): m = Module() # Create our clock domains. m.domains.sync = ClockDomain() m.domains.usb = ClockDomain() m.submodules.usb_reset = controller = PHYResetController() m.d.comb += [ ResetSignal("usb").eq(controller.phy_reset), self.usb_holdoff.eq(controller.phy_stop) ] # Attach Clock domains m.d.comb += [ ClockSignal(domain="sync").eq(self.clk_sync), ClockSignal(domain="usb").eq(self.clk_usb), ResetSignal("sync").eq(self.rst_sync), ] # Attach usb module m.submodules.usb0 = self.usb0 m.d.comb += [ # Wire up streams self.usb0.tx.valid.eq(self.tx.valid), self.usb0.tx.first.eq(self.tx.first), self.usb0.tx.last.eq(self.tx.last), self.usb0.tx.payload.eq(self.tx.payload), # -- self.tx.ready.eq(self.usb0.tx.ready), self.rx.valid.eq(self.usb0.rx.valid), self.rx.first.eq(self.usb0.rx.first), self.rx.last.eq(self.usb0.rx.last), self.rx.payload.eq(self.usb0.rx.payload), # -- self.usb0.rx.ready.eq(self.rx.ready), # ... and always connect by default. self.usb0.connect.eq(1) ] return m
def setup(validator: Optional[Base]): result = CliSetup( Module(), Core(validator), ClockDomain("ph1"), ClockSignal("ph1"), ) result.m.submodules.core = result.core result.m.domains.ph1 = result.ph1 result.ph1.rst = result.core.Rst return result
def elaborate(self, platform): m = Module() # Create our domains... m.domains.usb = ClockDomain() m.domains.usb_io = ClockDomain() m.domains.fast = ClockDomain() # ... and create our 12 MHz USB clock. m.submodules.pll = Instance( "SB_PLL40_CORE", i_REFERENCECLK=ClockSignal("sync"), i_RESETB=Const(1), i_BYPASS=Const(0), o_PLLOUTCORE=ClockSignal("usb"), # Create a 24 MHz PLL clock... p_FEEDBACK_PATH="SIMPLE", p_DIVR=0, p_DIVF=15, p_DIVQ=5, p_FILTER_RANGE=4, # ... and divide it by half to get 12 MHz. p_PLLOUT_SELECT="GENCLK_HALF") # We'll use our 48MHz clock for everything _except_ the usb_io domain... m.d.comb += [ ClockSignal("usb_io").eq(ClockSignal("sync")), ClockSignal("fast").eq(ClockSignal("sync")) ] return m
def elaborate(self, platform): m = Module() # Create our domains... m.domains.sync = ClockDomain() m.domains.usb = ClockDomain() m.domains.usb_io = ClockDomain() m.domains.fast = ClockDomain() # ... create our 48 MHz IO and 12 MHz USB clock... m.submodules.pll = Instance( "SB_PLL40_2F_CORE", i_REFERENCECLK=platform.request(platform.default_clk), i_RESETB=Const(1), i_BYPASS=Const(0), o_PLLOUTCOREA=ClockSignal("sync"), o_PLLOUTCOREB=ClockSignal("usb"), # Create a 48 MHz PLL clock... p_FEEDBACK_PATH="SIMPLE", p_PLLOUT_SELECT_PORTA="GENCLK", p_PLLOUT_SELECT_PORTB="SHIFTREG_0deg", p_DIVR=0, p_DIVF=47, p_DIVQ=4, p_FILTER_RANGE=1, ) # We'll use our 48MHz clock for everything _except_ the usb domain... m.d.comb += [ ClockSignal("usb_io").eq(ClockSignal("sync")), ClockSignal("fast").eq(ClockSignal("sync")) ] return m
def elaborate(self, platform: Platform): led1 = platform.request("led", 0) led2 = platform.request("led", 1) led3 = platform.request("led", 2) led4 = platform.request("led", 3) ft600_resource = platform.request("ft600") m = Module() # Connect pseudo power pins for the FT600 and DDR3 banks pseudo_power = platform.request("pseudo_power") m.d.comb += pseudo_power.ddr.o.eq(Repl(1, len(pseudo_power.ddr))) m.d.comb += pseudo_power.ft.o.eq(Repl(1, len(pseudo_power.ft))) m.submodules.pll = ECP5PLL(clock_signal_name="pll_clk25", clock_config=[ ECP5PLLConfig("sync", 25), ]) m.domains += ClockDomain("ft600") m.d.comb += ClockSignal("ft600").eq(ft600_resource.clk) m.submodules.ft600 = ft600 = DomainRenamer("ft600")(FT600( ft600_resource, )) m.submodules.fifo = fifo = AsyncFIFOBuffered(width=16, depth=2048, r_domain="ft600", w_domain="sync") # FT to Write FIFO m.d.comb += ft600.input_payload.eq(fifo.r_data) m.d.comb += fifo.r_en.eq(ft600.input_ready) m.d.comb += ft600.input_valid.eq(fifo.r_rdy) # Write data into FIFO m.d.comb += fifo.w_data.eq(0xABCD) m.d.comb += fifo.w_en.eq(1) led_counter = Signal(10) with m.If(fifo.w_rdy): m.d.sync += led_counter.eq(led_counter + 1) # Connect LEDs m.d.comb += led1.o.eq(ft600_resource.write) m.d.comb += led2.o.eq(ft600_resource.txe) m.d.comb += led3.o.eq(fifo.w_level > 2000) m.d.comb += led4.o.eq(led_counter[-1]) return m
def elaborate(self, platform): m = Module() self.invert = ControlSignal( reset=is_signal_inverted(platform, self.pad)) oserdes = m.submodules.oserdes = _OSerdes(data_width=self.bit_width, tristate_width=1, data_rate_oq="ddr", serdes_mode="master", data_rate_tq="buf") m.d.comb += oserdes.oce.eq(1) m.d.comb += oserdes.clk.eq(ClockSignal(self.ddr_domain)) m.d.comb += oserdes.clkdiv.eq(ClockSignal()) m.d.comb += oserdes.rst.eq(ResetSignal()) m.d.comb += Cat( oserdes.d[i] for i in (range(1, 9) if self.msb_first else reversed(range(1, 9)) )).eq(self.value ^ self.invert) m.d.comb += self.pad.eq(oserdes.oq) return m
def elaborate(self, platform): m = Module() if platform is not None: # platform.default_clk_frequency is in Hz coeff = self._calc_freq_coefficients( platform.default_clk_frequency / 1_000_000, self.freq_out) # clk_pin = platform.request(platform.default_clk) lock = Signal() pll = Instance( "SB_PLL40_CORE", p_FEEDBACK_PATH='SIMPLE', p_DIVR=coeff.divr, p_DIVF=coeff.divf, p_DIVQ=coeff.divq, p_FILTER_RANGE=0b001, p_DELAY_ADJUSTMENT_MODE_FEEDBACK='FIXED', p_FDA_FEEDBACK=0b0000, p_DELAY_ADJUSTMENT_MODE_RELATIVE='FIXED', p_FDA_RELATIVE=0b0000, p_SHIFTREG_DIV_MODE=0b00, p_PLLOUT_SELECT='GENCLK', p_ENABLE_ICEGATE=0b0, i_REFERENCECLK=ClockSignal(), o_PLLOUTCORE=ClockSignal(self.domain_name), i_RESETB=ResetSignal(), i_BYPASS=Const(0), o_LOCK=lock, ) rs = ResetSynchronizer(~lock, domain=self.domain_name) m.submodules += [pll, rs] m.domains += ClockDomain(self.domain_name) return m
def elaborate(self, platform): m = Module() # Get the SDRAM pins dir_dict = { "a":"-", "ba":"-", "cke":"-", "clk":"-", "clk_en":"-", "dq":"io", "dqm":"-", "cas":"-", "cs":"-", "ras":"-", "we":"-", } sdram = platform.request("sdram", dir=dir_dict) # Create the controller m.submodules.ctrl = ctrl = Sdram() m.d.comb += [ # Set the chip output pins sdram.a.eq(ctrl.sd_addr), sdram.dqm.eq(ctrl.sd_dqm), sdram.ba.eq(ctrl.sd_ba), sdram.cs.eq(ctrl.sd_cs), sdram.we.eq(ctrl.sd_we), sdram.ras.eq(ctrl.sd_ras), sdram.cas.eq(ctrl.sd_cas), sdram.clk_en.eq(1), sdram.clk.eq(ClockSignal("sdram_clk")), sdram.dq.o.eq(ctrl.sd_data_out), sdram.dq.oe.eq(ctrl.sd_data_dir), # Set the controller input pins ctrl.init.eq(self.init), ctrl.din.eq(self.data_in), ctrl.addr.eq(self.address), ctrl.we.eq(self.req_write), ctrl.oe.eq(self.req_read), ctrl.sync.eq(self.sync), ctrl.ds.eq(C(0b11,2)), ctrl.sd_data_in.eq(sdram.dq.i), # Set output pins self.data_out.eq(ctrl.dout) ] return m
def elaborate(self, platform): m = Module() # Generate our clock domains. clocking = LunaECP5DomainGenerator() m.submodules.clocking = clocking # Grab a reference to our debug-SPI bus. board_spi = synchronize(m, platform.request("debug_spi")) # Create our SPI-connected registers. m.submodules.spi_registers = spi_registers = SPIRegisterInterface( 7, 32) m.d.comb += spi_registers.spi.connect(board_spi) # Create our UMTI translator. ulpi = platform.request("sideband_phy") m.submodules.umti = umti = UMTITranslator(ulpi=ulpi) # Strap our power controls to be in VBUS passthrough by default, # on the target port. m.d.comb += [ platform.request("power_a_port").eq(0), platform.request("pass_through_vbus").eq(1), ] # Hook up our LEDs to status signals. m.d.comb += [ platform.request("led", 0).eq(umti.vbus_valid), platform.request("led", 1).eq(umti.session_valid), platform.request("led", 2).eq(umti.session_end), platform.request("led", 3).eq(umti.rx_active), platform.request("led", 4).eq(umti.rx_error) ] spi_registers.add_read_only_register(1, read=umti.last_rx_command) # For debugging: mirror some ULPI signals on the UIO. user_io = Cat( platform.request("user_io", i, dir="o") for i in range(0, 4)) m.d.comb += [ user_io[0].eq(ClockSignal("ulpi")), user_io[1].eq(ulpi.dir), user_io[2].eq(ulpi.nxt), user_io[3].eq(ulpi.stp), ] # Return our elaborated module. return m
def elaborate(self, platform): m = Module() m.submodules.demoaxi_i = Instance( 'demoaxi', p_C_S_AXI_DATA_WIDTH=self.data_w, p_C_S_AXI_ADDR_WIDTH=self.addr_w, i_S_AXI_ACLK=ClockSignal(self.domain), i_S_AXI_ARESETN=~ResetSignal(self.domain), **get_ports_for_instance(self.axilite, prefix='S_AXI_'), ) if isinstance(platform, Platform): for d in self.DEPENDENCIES: add_verilog_file(platform, d) return m
def elaborate(self, platform): m = Module() iserdes = m.submodules.iserdes = _ISerdes( data_width=self.bit_width, data_rate="ddr", serdes_mode="master", interface_type="networking", num_ce=1, iobDelay="ifd", ) m.d.comb += iserdes.ddly.eq(self.pad) m.d.comb += iserdes.ce[1].eq(1) m.d.comb += iserdes.clk.eq(ClockSignal(self.ddr_domain)) m.d.comb += iserdes.clkb.eq(~ClockSignal(self.ddr_domain)) m.d.comb += iserdes.rst.eq(ResetSignal()) m.d.comb += iserdes.clkdiv.eq(ClockSignal()) m.d.comb += self.output.eq( Cat(iserdes.q[i] for i in (range(1, 9) if self. msb_first else reversed(list(range(1, 9)))))) m.d.comb += iserdes.bitslip.eq(self.bitslip) return m
def formal(cls) -> Tuple[Module, List[Signal]]: m = Module() ph = ClockDomain("ph") clk = ClockSignal("ph") m.domains += ph m.d.sync += clk.eq(~clk) s = IC_reg32_with_mux(clk="ph", N=2, faster=True) m.submodules += s sync_clk = ClockSignal("sync") sync_rst = ResetSignal("sync") with m.If(Rose(clk)): with m.Switch(~Past(s.n_sel)): with m.Case(0b11): m.d.comb += Assert(0) with m.Case(0b01): m.d.comb += Assert(s.q == Past(s.d[0])) with m.Case(0b10): m.d.comb += Assert(s.q == Past(s.d[1])) with m.Default(): m.d.comb += Assert(s.q == Past(s.q)) # Make sure the clock is clocking m.d.comb += Assume(sync_clk == ~Past(sync_clk)) # Don't want to test what happens when we reset. m.d.comb += Assume(~sync_rst) m.d.comb += Assume(~ResetSignal("ph")) m.d.comb += Assume(s.n_sel != 0) return m, [sync_clk, sync_rst, s.d[0], s.d[1], s.n_sel, s.q]
def elaborate(self, platform): m = Module() # Create the component parts of our ULPI interfacing hardware. register_window = ULPIRegisterWindow() rxevent_decoder = ULPIRxEventDecoder(ulpi_bus=self.ulpi) m.submodules.register_window = register_window m.submodules.rxevent_decoder = rxevent_decoder # Connect our ULPI control signals to each of our subcomponents. m.d.comb += [ # Drive the bus whenever the target PHY isn't. self.ulpi.data.oe.eq(~self.ulpi.dir), # Generate our busy signal. self.busy.eq(register_window.busy), # Connect up our clock and reset signals. self.ulpi.clk.eq(ClockSignal("ulpi")), self.ulpi.rst.eq(ResetSignal("ulpi")), # Connect our data inputs to the event decoder. # Note that the event decoder is purely passive. rxevent_decoder.register_operation_in_progress.eq( register_window.busy), self.last_rx_command.eq(rxevent_decoder.last_rx_command), # Connect our signals to our register window. register_window.ulpi_data_in.eq(self.ulpi.data.i), register_window.ulpi_dir.eq(self.ulpi.dir), register_window.ulpi_next.eq(self.ulpi.nxt), self.ulpi.data.o.eq(register_window.ulpi_data_out), self.ulpi.stp.eq(register_window.ulpi_stop), register_window.address.eq(self.address), register_window.write_data.eq(self.write_data), register_window.read_request.eq(self.manual_read), register_window.write_request.eq(self.manual_write), self.read_data.eq(register_window.read_data) ] # Connect our RxEvent status signals from our RxEvent decoder. for signal_name in self.RXEVENT_STATUS_SIGNALS: signal = getattr(rxevent_decoder, signal_name) m.d.comb += self.__dict__[signal_name].eq(signal) return m
def elaborate(self, platform): m = Module() # pins ft_clkout_i = platform.request("ft_clkout_i") ft_wr_n_o = platform.request("ft_wr_n_o") ft_wr_n_o.o.reset = 1 ft_txe_n_i = platform.request("ft_txe_n_i") ft_suspend_n_i = platform.request("ft_suspend_n_i") ft_oe_n_o = platform.request("ft_oe_n_o") ft_rd_n_o = platform.request("ft_rd_n_o") ft_siwua_n_o = platform.request("ft_siwua_n_o") ft_data_io = platform.request("ft_data_io") ext1 = platform.request("ext1") pa_en_n_o = platform.request("pa_en_n_o") # clock domains m.domains += ClockDomain("clk60") m.d.comb += ClockSignal("clk60").eq(ft_clkout_i.i) # signals ctr = Signal(8, reset=0) ctr_last = Signal(8, reset=0) ft_txe_last = Signal(1, reset=0) # sync + comb logic with m.If(~ft_txe_n_i.i & ft_suspend_n_i.i): m.d.clk60 += [ft_wr_n_o.o.eq(0), ctr.eq(ctr + 1), ctr_last.eq(ctr)] with m.Elif(ft_txe_n_i.i & ~ft_txe_last): m.d.clk60 += [ctr.eq(ctr_last), ft_wr_n_o.o.eq(1)] with m.Else(): m.d.clk60 += [ft_wr_n_o.o.eq(1)] m.d.clk60 += [ft_txe_last.eq(ft_txe_n_i.i)] m.d.comb += [ ft_oe_n_o.o.eq(1), ft_rd_n_o.o.eq(1), ft_siwua_n_o.o.eq(1), ft_data_io.o.eq(ctr), ft_data_io.oe.eq(1), pa_en_n_o.o.eq(1), ] return m
def add_ulpi_registers(self, m, platform, *, ulpi_bus, register_base): """ Adds a set of ULPI registers to the active design. """ target_ulpi = platform.request(ulpi_bus) ulpi_reg_window = ULPIRegisterWindow() m.submodules += ulpi_reg_window m.d.comb += [ ulpi_reg_window.ulpi_data_in .eq(target_ulpi.data.i), ulpi_reg_window.ulpi_dir .eq(target_ulpi.dir), ulpi_reg_window.ulpi_next .eq(target_ulpi.nxt), target_ulpi.clk .eq(ClockSignal("usb")), target_ulpi.rst .eq(ResetSignal("usb")), target_ulpi.stp .eq(ulpi_reg_window.ulpi_stop), target_ulpi.data.o .eq(ulpi_reg_window.ulpi_data_out), target_ulpi.data.oe .eq(~target_ulpi.dir) ] register_address_change = Signal() register_value_change = Signal() # ULPI register address. spi_registers = m.submodules.spi_registers spi_registers.add_register(register_base + 0, write_strobe=register_address_change, value_signal=ulpi_reg_window.address, size=6 ) m.submodules.clocking.stretch_sync_strobe_to_usb(m, strobe=register_address_change, output=ulpi_reg_window.read_request, ) # ULPI register value. spi_registers.add_sfr(register_base + 1, read=ulpi_reg_window.read_data, write_signal=ulpi_reg_window.write_data, write_strobe=register_value_change ) m.submodules.clocking.stretch_sync_strobe_to_usb(m, strobe=register_value_change, output=ulpi_reg_window.write_request )
def elaborate(self, platform): """ Generate the SF tester. """ m = Module() # Grab our I/O connectors. clk = platform.request("clk2") port_b = platform.request("port_b_bus", dir="o") # TODO: also blink r0.2+'s LEDs # Grab our clock signal, and attach it to the main clock domain. m.domains.sync = ClockDomain() m.d.comb += ClockSignal().eq(clk.i) # Increment port_b every clock cycle, for now. m.d.sync += port_b.o.eq(port_b.o + 1) # Return our elaborated module. return m
def peripherals_connect_hook(platform, top_fragment: Fragment, sames): from naps.cores.axi import AxiEndpoint, AxiLitePeripheralConnector, AxiFullToLiteBridge, AxiInterconnect if platform.peripherals: m = Module() platform.ps7.fck_domain(domain_name="axi_lite", requested_frequency=10e6) if not hasattr( platform, "is_sim"): # we are not in a simulation platform axi_full_port: AxiEndpoint = platform.ps7.get_axi_gp_master( ClockSignal(self.csr_domain)) axi_lite_bridge = m.submodules.axi_lite_bridge = DomainRenamer( self.csr_domain)(AxiFullToLiteBridge(axi_full_port)) axi_lite_master = axi_lite_bridge.lite_master else: # we are in a simulation platform axi_lite_master = AxiEndpoint(addr_bits=32, data_bits=32, lite=True) self.axi_lite_master = axi_lite_master if use_axi_interconnect: interconnect = m.submodules.interconnect = DomainRenamer( self.csr_domain)(AxiInterconnect(axi_lite_master)) for peripheral in platform.peripherals: connector = DomainRenamer(self.csr_domain)( AxiLitePeripheralConnector(peripheral)) m.d.comb += interconnect.get_port().connect_downstream( connector.axi) m.submodules += connector else: aggregator = PeripheralsAggregator() for peripheral in platform.peripherals: aggregator.add_peripheral(peripheral) connector = DomainRenamer(self.csr_domain)( AxiLitePeripheralConnector(aggregator)) m.d.comb += axi_lite_master.connect_downstream( connector.axi) m.submodules.connector = connector platform.to_inject_subfragments.append((m, self.csr_domain))
def process(self, m: Module): # Decode instruction m.d.comb += [ self._opcode.eq(self.state._instr[:7]), self._rs1.eq(self.state._instr[15:20]), self._rs2.eq(self.state._instr[20:25]), self._rd.eq(self.state._instr[7:12]), self._funct3.eq(self.state._instr[12:15]), self._funct7.eq(self.state._instr[25:]), self._alu_func[:3].eq(self._funct3), self._alu_func[3].eq(self._funct7[5]), self._funct12.eq(self.state._instr[20:]), ] if (self.chips): self.decode_imm_chips(m) else: self.decode_imm(m) # We don't evaluate the instruction for badness until after it's loaded. ph2r_clk = ClockSignal("ph2r") m.d.comb += self.bad_instr.eq(ph2r_clk & ( (self.state._instr[:16] == 0) | (self.state._instr == 0xFFFFFFFF))) with m.Switch(self._funct3): with m.Case(BranchCond.EQ): m.d.comb += self.branch_cond.eq(self.state._stored_alu_eq == 1) with m.Case(BranchCond.NE): m.d.comb += self.branch_cond.eq(self.state._stored_alu_eq == 0) with m.Case(BranchCond.LT): m.d.comb += self.branch_cond.eq(self.state._stored_alu_lt == 1) with m.Case(BranchCond.GE): m.d.comb += self.branch_cond.eq(self.state._stored_alu_lt == 0) with m.Case(BranchCond.LTU): m.d.comb += self.branch_cond.eq( self.state._stored_alu_ltu == 1) with m.Case(BranchCond.GEU): m.d.comb += self.branch_cond.eq( self.state._stored_alu_ltu == 0)
def peripherals_connect_hook(platform, top_fragment: Fragment, sames): if platform.peripherals: m = Module() platform.ps7.fck_domain(domain_name="axi_lite", requested_frequency=100e6) if not hasattr(platform, "is_sim"): # we are not in a simulation platform axi_full_port: AxiEndpoint = platform.ps7.get_axi_gp_master(ClockSignal("axi_lite")) axi_lite_bridge = m.submodules.axi_lite_bridge = DomainRenamer("axi_lite")( AxiFullToLiteBridge(axi_full_port) ) axi_lite_master = axi_lite_bridge.lite_master else: # we are in a simulation platform axi_lite_master = AxiEndpoint(addr_bits=32, data_bits=32, master=True, lite=True) self.axi_lite_master = axi_lite_master interconnect = m.submodules.interconnect = DomainRenamer("axi_lite")( AxiInterconnect(axi_lite_master) ) for peripheral in platform.peripherals: controller = DomainRenamer("axi_lite")(AxiLitePeripheralConnector(peripheral)) m.d.comb += interconnect.get_port().connect_slave(controller.axi) m.submodules += controller platform.to_inject_subfragments.append((m, "axi_lite"))