def test_generator(self):
'''
This test creates wrappers for 2 IPs
and connects them in a separate module
'''
from fpga_topwrap.ipwrapper import IPWrapper
from fpga_topwrap.ipconnect import IPConnect
# wrap IPs
dma = IPWrapper(yamlfile='tests/data/DMATop.yaml', ip_name='DMATop')
disp = IPWrapper(yamlfile='tests/data/axi_dispctrl_v1_0.yaml',
ip_name='axi_dispctrl_v1_0')
dma_fragment = Fragment.get(dma, None)
disp_fragment = Fragment.get(disp, None)
assert verilog.convert(dma_fragment,
name=dma.top_name,
ports=dma.get_ports())
assert verilog.convert(disp_fragment,
name=disp.top_name,
ports=disp.get_ports())
# connect the IPs in another module
connector = IPConnect()
connector.add_ip(dma)
connector.add_ip(disp)
connector.connect_interfaces('AXIS_m0', dma.top_name, 'AXIS_s0',
disp.top_name)
# connect output of disp to two inputs of dma
connector.connect_ports('io_sync_writerSync', dma.top_name, 'HSYNC_O',
disp.top_name)
connector.connect_ports('io_sync_readerSync', dma.top_name, 'HSYNC_O',
disp.top_name)
fragment = Fragment.get(connector, None)
assert verilog.convert(fragment, name='top')
def build(self,
build_dir='build',
template=None,
sources_dir=None,
top_module_name='project_top',
part=None):
# This class is used for generating FuseSoC Core file
fuse = FuseSocBuilder(part)
for ip in self._ips.values():
filename = ip.top_name + '.v'
fuse.add_source(filename, 'verilogSource')
target_file = open(path.join(build_dir, filename), 'w')
fragment = Fragment.get(ip, None)
output = verilog.convert(fragment,
name=ip.top_name,
ports=ip.get_ports())
target_file.write(output)
fuse.add_source(top_module_name + '.v', 'verilogSource')
fuse.build(path.join(build_dir, 'top.core'), sources_dir=sources_dir)
target_file = open(path.join(build_dir, top_module_name + '.v'), 'w')
fragment = Fragment.get(self, None)
output = verilog.convert(fragment,
name=top_module_name,
ports=self.get_ports())
target_file.write(output)
def assert_formal(spec, mode="bmc", depth=1):
functions = []
test_class = None
caller_path = ""
stack = inspect.stack()
for frame in stack[1:]:
if "unittest" in frame.filename:
filename = "__".join(reversed(functions))
if test_class:
filename = f'{test_class}__{filename}'
break
functions.append(frame.function)
try:
test_class = frame.frame.f_locals['self'].__class__.__name__
except:
pass
caller_path = frame.filename
target_dir = Path(caller_path).parent / ".sim_results"
target_dir.mkdir(exist_ok=True)
if (target_dir / filename).exists():
rmtree(target_dir / filename)
if mode == "hybrid":
# A mix of BMC and k-induction, as per personal communication with Claire Wolf.
script = "setattr -unset init w:* a:nmigen.sample_reg %d"
mode = "bmc"
else:
script = ""
config = textwrap.dedent("""\
[options]
mode {mode}
depth {depth}
wait on
[engines]
smtbmc
[script]
read_ilang top.il
prep
{script}
[file top.il]
{rtlil}
""").format(mode=mode,
depth=depth,
script=script,
rtlil=rtlil.convert(Fragment.get(spec,
platform=FormalPlatform)))
with subprocess.Popen([require_tool("sby"), "-f", "-d", filename],
cwd=str(target_dir),
universal_newlines=True,
stdin=subprocess.PIPE,
stdout=subprocess.PIPE) as proc:
stdout, stderr = proc.communicate(config)
if proc.returncode != 0:
assert False, "Formal verification failed:\n" + stdout + "\n\n" + f"vcd: {str(target_dir / filename)}/engine_0/trace.vcd"
def generate_verilog(verilog_file, design, platform, name='top', ports=(), vcd_file=None):
fragment = Fragment.get(design, platform)
print(name, ports)
output = verilog.convert(fragment, name=name, ports=ports)
with open(verilog_file, 'w') as f:
f.write('`timescale 1ns/1ps\n')
f.write(output)
if vcd_file:
vcd_file = os.path.abspath(vcd_file)
f.write(verilog_waveforms.format(vcd_file, name).replace('\\', '/'))
caller_file = Path(inspect.stack()[1].filename)
name = caller_file.stem
build_dir = "build" / Path(f"{name}_{args.device}_{args.soc}")
fatbitstream_name = build_dir / f"{name}.zip"
if not (args.program or args.build or args.elaborate or args.run):
print("no action specified")
parser.print_help(sys.stderr)
exit(-1)
if args.elaborate or args.build:
timer.start_task("elaboration")
if args.soc != 'None':
elaborated = platform.prepare_soc(top_class())
else:
elaborated = Fragment.get(top_class(), platform)
timer.end_task()
if args.build:
needs_rebuild = True
elaborated_repr = fragment_repr(elaborated)
cache_hash = hashlib.sha256(elaborated_repr.encode()).hexdigest()
gateware_build_dir = build_dir / "gateware" / cache_hash
cache_key_path = gateware_build_dir / "cache_key.txt"
if cache_key_path.exists():
old_repr = cache_key_path.read_text()
if args.force_cache: