def sample_in_process():
def send_sample(x):
#280 yield design.samples_in.i_valid.eq(True)
#280 yield design.samples_in.i_data.eq(x)
yield i_valid.eq(True)
yield i_data.eq(x)
yield
for i in range(N + 2):
if (yield design.samples_in.received()):
break
yield
#280 yield design.samples_in.i_valid.eq(False)
yield i_valid.eq(False)
R = cfg.osc_rate // cfg.out_rate
assert isinstance(R, int)
yield from delay(3)
# for i in range(200):
# x = i == 10 and 32767 or i
# x = i
# yield from send_sample(x)
# yield from delay(R - 1)
freq = 1000
nsamp_in = int(4 * cfg.osc_rate // freq)
for i in range(nsamp_in):
from math import sin, tau
y = sin(tau * i * freq / cfg.osc_rate)
y *= 0.95
y = (y + 1) % 1
y = 2 * y - 1
y = int(32767 * y)
yield from send_sample(y)
yield from delay(R - 1)
def data_source():
class Pause:
pass
data = [
0x93,
60,
64, # note on C4
Pause,
67,
96, # note on G4 (running status)
Pause,
0x83,
60,
32, # note off C4
0x93,
67,
0, # note off G4 (note on w/velocity 0)
]
for i, d in enumerate(data):
if d is Pause:
yield from delay(5)
else:
yield design.serial_data.eq(d)
yield design.serial_rdy.eq(True)
yield
yield design.serial_rdy.eq(False)
yield from delay(i % 3)
yield from delay(2)
def send_char():
char = 'Q'
yield from delay(2)
yield design.tx_data.eq(ord(char))
yield design.tx_trg.eq(True)
yield
yield design.tx_trg.eq(False)
yield from delay(10 * divisor + 2)
def trigger_proc():
trg = top.trigger
for i in range(10):
yield trg.eq(True)
yield
if i % 3:
yield trg.eq(False)
yield from delay((i + 1) % 3)
yield trg.eq(False)
yield from delay(3)
def note_sink():
NoteMsg = namedtuple('NoteMsg', 'onoff channel note velocity')
expected = [
NoteMsg(True, 3, 60, 64),
NoteMsg(True, 3, 67, 96),
NoteMsg(False, 3, 60, 32),
NoteMsg(False, 3, 67, 0),
]
expected_index = 0
yield Passive()
#280
yield i_note_ready.eq(False)
while True:
valid = yield design.note_msg_out.o_valid
#280
ready = yield i_note_ready
if valid and not ready:
yield from delay(expected_index)
#280
yield i_note_ready.eq(True)
elif valid and ready:
#280
yield i_note_ready.eq(False)
actual = NoteMsg(
(yield design.note_msg_out.o_data.onoff),
(yield design.note_msg_out.o_data.channel),
(yield design.note_msg_out.o_data.note),
(yield design.note_msg_out.o_data.velocity),
)
assert expected_index < len(expected)
assert actual == expected[expected_index], (
f'expected {expected[expected_index]}, got {actual}'
)
expected_index += 1
yield
def recv_char():
char = 'Q'
char = chr(0x95) # Test high bit
yield design.rx_pin.eq(1)
yield from delay(3)
for i in range(2):
# Start bit
yield design.rx_pin.eq(0)
yield from delay(divisor)
# Data bits
for i in range(8):
yield design.rx_pin.eq(ord(char) >> i & 1)
yield from delay(divisor)
# Stop bit
yield design.rx_pin.eq(1)
yield from delay(divisor)
yield from delay(2)
def note_proc():
# from C5 to C7 by major thirds:
for note in range(60 + 12, 60 + 36 + 1, 4):
for _ in range(200):
yield design.note_in.eq(note)
yield design.pw_in.eq(50 * note - 360)
yield
yield design.sync_in.eq(0)
yield from delay(divisor - 1)
def note_proc():
# from C5 to C7 by major thirds:
for note in range(60 + 12, 60 + 36 + 1, 4):
pw = (50 * note - 360) % 128
print(f'note = {note}, pw = {pw}')
yield design.pw_in.eq(pw)
yield design.note_in.i_valid.eq(True)
yield design.note_in.i_data.note.eq(note)
for _ in range(200):
yield
yield from delay(divisor - 1)
yield design.note_in.i_valid.eq(False)
def sample_out_process():
def recv_sample():
#280 yield design.samples_out.i_ready.eq(True)
yield i_ready.eq(True)
for i in range(N + 2):
yield
if (yield design.samples_out.o_valid):
break
#280 yield design.samples_out.i_ready.eq(False)
yield i_ready.eq(False)
yield Passive()
while True:
yield from recv_sample()
yield from delay(M)
def sim_notes():
notes = [
(1, 0, 60, 100), # wrong channel
(1, 3, 62, 99), # ok, play D4
(1, 3, 64, 98), # ok, play E4
(1, 0, 64, 97), # wrong channel
(0, 3, 62, 0), # wrong note
(0, 3, 64, 0), # ok, stop
]
for (on, chan, key, vel) in notes:
yield i_valid.eq(True)
yield i_onoff.eq(on)
yield i_channel.eq(chan)
yield i_note.eq(key)
yield i_velocity.eq(vel)
yield
yield i_valid.eq(False)
yield from delay(3)
def sim_notes():
notes = [
(1, 0, 60, 100), # wrong channel
(1, 3, 62, 99), # ok, play D4
(1, 3, 64, 98), # ok, play E4
(1, 0, 64, 97), # wrong channel
(0, 3, 62, 0), # wrong note
(0, 3, 64, 0), # ok, stop
]
for (on, chan, key, vel) in notes:
yield design.note_on_rdy.eq(on)
yield design.note_off_rdy.eq(not on)
yield design.note_chan.eq(chan)
yield design.note_key.eq(key)
yield design.note_vel.eq(vel)
yield
yield design.note_on_rdy.eq(False)
yield design.note_off_rdy.eq(False)
yield from delay(3)