print(output_layer_value) # -------------------- # (5) Convert the NNgen dataflow to a hardware description (Verilog HDL and IP-XACT) # -------------------- silent = False axi_datawidth = 32 # to Veriloggen object # targ = ng.to_veriloggen([output_layer], 'hello_nngen', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # to IP-XACT (the method returns Veriloggen object, as well as to_veriloggen) targ = ng.to_ipxact([output_layer], 'hello_nngen', silent=silent, config={'maxi_datawidth': axi_datawidth}) print('# IP-XACT was generated. Check the current directory.') # to Verilog HDL RTL (the method returns a source code text) # rtl = ng.to_verilog([output_layer], 'hello_nngen', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # -------------------- # (6) Save the quantized weights # -------------------- # convert weight values to a memory image: # on a real FPGA platform, this image will be used as a part of the model definition. param_filename = 'hello_nngen.npy'
def run( act_dtype=ng.int16, weight_dtype=ng.int8, bias_dtype=ng.int32, scale_dtype=ng.int8, with_batchnorm=True, disable_fusion=False, conv2d_par_ich=1, conv2d_par_och=1, conv2d_par_col=1, conv2d_par_row=1, conv2d_concur_och=None, conv2d_stationary='filter', pool_par=1, elem_par=1, chunk_size=64, axi_datawidth=32, silent=False, filename=None, # simtype='iverilog', # simtype='verilator', simtype=None, # no RTL simulation outputfile=None): # input mean and standard deviation imagenet_mean = np.array([0.485, 0.456, 0.406]).astype(np.float32) imagenet_std = np.array([0.229, 0.224, 0.225]).astype(np.float32) act_shape = (1, 224, 224, 3) if not with_batchnorm: raise ValueError('with_batchnorm must be True for ResNet18.') # pytorch model model = torchvision.models.resnet18(pretrained=True) # Pytorch to ONNX onnx_filename = 'resnet18_imagenet.onnx' dummy_input = torch.randn(*act_shape).transpose(1, 3) input_names = ['act'] output_names = ['out'] model.eval() torch.onnx.export(model, dummy_input, onnx_filename, input_names=input_names, output_names=output_names) # -------------------- # (1) Represent a DNN model as a dataflow by NNgen operators # -------------------- # ONNX to NNgen dtypes = {} (outputs, placeholders, variables, constants, operators) = ng.from_onnx(onnx_filename, value_dtypes=dtypes, default_placeholder_dtype=act_dtype, default_variable_dtype=weight_dtype, default_constant_dtype=weight_dtype, default_operator_dtype=act_dtype, default_scale_dtype=scale_dtype, default_bias_dtype=bias_dtype, disable_fusion=disable_fusion) # -------------------- # (2) Assign quantized weights to the NNgen operators # -------------------- if act_dtype.width > 8: act_scale_factor = 128 else: act_scale_factor = int(round(2**(act_dtype.width - 1) * 0.5)) input_scale_factors = {'act': act_scale_factor} input_means = {'act': imagenet_mean * act_scale_factor} input_stds = {'act': imagenet_std * act_scale_factor} ng.quantize(outputs, input_scale_factors, input_means, input_stds) # -------------------- # (3) Assign hardware attributes # -------------------- for op in operators.values(): if isinstance(op, ng.conv2d): op.attribute(par_ich=conv2d_par_ich, par_och=conv2d_par_och, par_col=conv2d_par_col, par_row=conv2d_par_row, concur_och=conv2d_concur_och, stationary=conv2d_stationary) if isinstance(op, (ng.avg_pool, ng.max_pool, ng.avg_pool_serial, ng.max_pool_serial)): op.attribute(par=pool_par) if ng.is_elementwise_operator(op): op.attribute(par=elem_par) # -------------------- # (4) Verify the DNN model behavior by executing the NNgen dataflow as a software # -------------------- act = placeholders['act'] out = outputs['out'] # verification data img = np.array(PIL.Image.open('car.png').convert('RGB')).astype(np.float32) img = img.reshape([1] + list(img.shape)) img = img / 255 img = (img - imagenet_mean) / imagenet_std # execution on pytorch model_input = np.broadcast_to(img, act_shape) if act.perm is not None: model_input = np.transpose(model_input, act.reversed_perm) model.eval() model_out = model(torch.from_numpy(model_input)).detach().numpy() if act.perm is not None and len(model_out.shape) == len(act.shape): model_out = np.transpose(model_out, act.perm) scaled_model_out = model_out * out.scale_factor # software-based verification vact = img * act_scale_factor vact = np.clip(vact, -1.0 * (2**(act.dtype.width - 1) - 1), 1.0 * (2**(act.dtype.width - 1) - 1)) vact = np.round(vact).astype(np.int64) vact = np.broadcast_to(vact, act_shape) # compare outputs of hidden layers relu_op = [ v for k, v in operators.items() if isinstance(v, ng.conv2d) and not isinstance(v, ng.matmul) ][0] maxpool_op = [ v for k, v in operators.items() if isinstance(v, (ng.max_pool, ng.max_pool_serial)) ][0] relu_ops = [v for k, v in operators.items() if isinstance(v, ng.relu)] layer1_0_op = relu_ops[0] layer1_op = relu_ops[1] layer2_0_op = relu_ops[2] layer2_op = relu_ops[3] layer3_0_op = relu_ops[4] layer3_op = relu_ops[5] layer4_0_op = relu_ops[6] layer4_op = relu_ops[7] avgpool_op = [ v for k, v in operators.items() if isinstance(v, (ng.avg_pool, ng.avg_pool_serial)) ][0] fc_op = [v for k, v in operators.items() if isinstance(v, ng.matmul)][0] sub_ops = [ relu_op, maxpool_op, layer1_0_op, layer1_op, layer2_0_op, layer2_op, layer3_0_op, layer3_op, layer4_0_op, layer4_op, avgpool_op, fc_op ] sub_outs = ng.eval(sub_ops, act=vact) sub_outs = [sub_out.transpose([0, 3, 1, 2]) for sub_out in sub_outs[:-1]] + sub_outs[-1:] sub_scale_factors = [sub_op.scale_factor for sub_op in sub_ops] model.eval() model_relu_out = nn.Sequential(model.conv1, model.bn1, model.relu)( torch.from_numpy(model_input)).detach().numpy() model_maxpool_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool)(torch.from_numpy(model_input)).detach().numpy() # class model_layer1_0(nn.Module): # def __init__(self): # super(model_layer1_0, self).__init__() # self.conv1 = model.conv1 # self.bn1 = model.bn1 # self.relu = model.relu # self.maxpool = model.maxpool # self.layer1_0 = model.layer1[0] # # def forward(self, x): # x = self.relu(self.bn1(self.conv1(x))) # x = self.maxpool(x) # x = self.layer1_0(x) # return x # # model_layer1_0_out = model_layer1_0()(torch.from_numpy(model_input)).detach().numpy() model_layer1_0_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1[0])(torch.from_numpy(model_input)).detach().numpy() model_layer1_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1)(torch.from_numpy(model_input)).detach().numpy() model_layer2_0_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2[0])(torch.from_numpy(model_input)).detach().numpy() model_layer2_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2)(torch.from_numpy(model_input)).detach().numpy() model_layer3_0_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2, model.layer3[0])(torch.from_numpy(model_input)).detach().numpy() model_layer3_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2, model.layer3)(torch.from_numpy(model_input)).detach().numpy() model_layer4_0_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2, model.layer3, model.layer4[0])(torch.from_numpy(model_input)).detach().numpy() model_layer4_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2, model.layer3, model.layer4)(torch.from_numpy(model_input)).detach().numpy() model_avgpool_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2, model.layer3, model.layer4, model.avgpool)(torch.from_numpy(model_input)).detach().numpy() class Flatten(nn.Module): def forward(self, input): return input.view(input.size(0), -1) model_fc_out = nn.Sequential( model.conv1, model.bn1, model.relu, model.maxpool, model.layer1, model.layer2, model.layer3, model.layer4, model.avgpool, Flatten(), model.fc)(torch.from_numpy(model_input)).detach().numpy() model_outs = [ model_relu_out, model_maxpool_out, model_layer1_0_out, model_layer1_out, model_layer2_0_out, model_layer2_out, model_layer3_0_out, model_layer3_out, model_layer4_0_out, model_layer4_out, model_avgpool_out, model_fc_out ] scaled_outs = [ model_out * scale_factor for model_out, scale_factor in zip(model_outs, sub_scale_factors) ] max_diffs = [ model_out.max() / sub_out.max() for model_out, sub_out in zip(scaled_outs, sub_outs) ] overflows = [ np.sum(np.abs(sub_out) >= abs(2**(sub_op.dtype.width - 1) - 1)) for sub_op, sub_out in zip(sub_ops, sub_outs) ] mean_square_errors = [ np.sum((sub_out - model_out)**2) / sub_out.size for model_out, sub_out in zip(scaled_outs, sub_outs) ] corrcoefs = [ np.corrcoef(model_out.reshape([-1]), sub_out.reshape([-1])) for model_out, sub_out in zip(model_outs, sub_outs) ] # compare prediction results eval_outs = ng.eval([out], act=vact) vout = eval_outs[0] mean_square_error = np.sum((vout - scaled_model_out)**2) / vout.size corrcoef = np.corrcoef(model_out.reshape([-1]), vout.reshape([-1])) class_index = json.load(open('imagenet_class_index.json', 'r')) labels = {int(key): value for (key, value) in class_index.items()} mout = scaled_model_out for bat in range(mout.shape[0]): m_top10 = list( sorted(enumerate(mout[bat]), key=lambda x: x[1], reverse=True))[:10] m_top10_indexes = [index for index, value in m_top10] v_top10 = list( sorted(enumerate(vout[bat]), key=lambda x: x[1], reverse=True))[:10] v_top10_indexes = [index for index, value in v_top10] num_hit = 0 score = 0 for index, value in m_top10: print("# mout: %s (%d) = %f" % (str(labels[index]), index, value)) for index, value in v_top10: print("# vout: %s (%d) = %d" % (str(labels[index]), index, value)) if index in m_top10_indexes: num_hit += 1 score += 10 - abs( m_top10_indexes.index(index) - v_top10_indexes.index(index)) print("# top-10 hit: %d" % num_hit) print("# top-10 score: %d" % score) # breakpoint() # -------------------- # (5) Convert the NNgen dataflow to a hardware description (Verilog HDL and IP-XACT) # -------------------- # to Veriloggen object # targ = ng.to_veriloggen([out], 'resnet18', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # to IP-XACT (the method returns Veriloggen object, as well as to_veriloggen) targ = ng.to_ipxact([out], 'resnet18', silent=silent, config={'maxi_datawidth': axi_datawidth}) # to Verilog HDL RTL (the method returns a source code text) # rtl = ng.to_verilog([out], 'resnet18', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # -------------------- # (6) Simulate the generated hardware by Veriloggen and Verilog simulator # -------------------- if simtype is None: sys.exit() # to memory image param_data = ng.export_ndarray([out], chunk_size) param_bytes = len(param_data) variable_addr = int(math.ceil( (act.addr + act.memory_size) / chunk_size)) * chunk_size check_addr = int(math.ceil( (variable_addr + param_bytes) / chunk_size)) * chunk_size tmp_addr = int(math.ceil( (check_addr + out.memory_size) / chunk_size)) * chunk_size memimg_datawidth = 32 # mem = np.zeros([1024 * 1024 * 256 // (memimg_datawidth // 8)], dtype=np.int64) mem = np.zeros([1024 * 1024 * 1024 // (memimg_datawidth // 8)], dtype=np.int16) mem = mem + [100] # placeholder axi.set_memory( mem, vact, memimg_datawidth, act_dtype.width, act.addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), conv2d_par_ich)) # parameters (variable and constant) axi.set_memory(mem, param_data, memimg_datawidth, 8, variable_addr) # verification data axi.set_memory( mem, vout, memimg_datawidth, act_dtype.width, check_addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), conv2d_par_och)) # test controller m = Module('test') params = m.copy_params(targ) ports = m.copy_sim_ports(targ) clk = ports['CLK'] resetn = ports['RESETN'] rst = m.Wire('RST') rst.assign(Not(resetn)) # AXI memory model if outputfile is None: outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out' memimg_name = 'memimg_' + outputfile memory = axi.AxiMemoryModel(m, 'memory', clk, rst, datawidth=axi_datawidth, memimg=mem, memimg_name=memimg_name, memimg_datawidth=memimg_datawidth) memory.connect(ports, 'maxi') # AXI-Slave controller _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True) _saxi.connect(ports, 'saxi') # timer time_counter = m.Reg('time_counter', 32, initval=0) seq = Seq(m, 'seq', clk, rst) seq(time_counter.inc()) def ctrl(): for i in range(100): pass ng.sim.set_global_addrs(_saxi, tmp_addr) start_time = time_counter.value ng.sim.start(_saxi) print('# start') ng.sim.wait(_saxi) end_time = time_counter.value print('# end') print('# execution cycles: %d' % (end_time - start_time)) # verify ok = True for bat in range(out.shape[0]): for x in range(out.shape[1]): orig = memory.read_word(bat * out.aligned_shape[1] + x, out.addr, act_dtype.width) check = memory.read_word(bat * out.aligned_shape[1] + x, check_addr, act_dtype.width) if vthread.verilog.NotEql(orig, check): print('NG (', bat, x, ') orig: ', orig, ' check: ', check) ok = False else: print('OK (', bat, x, ') orig: ', orig, ' check: ', check) if ok: print('# verify: PASSED') else: print('# verify: FAILED') vthread.finish() th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl) fsm = th.start() uut = m.Instance(targ, 'uut', params=m.connect_params(targ), ports=m.connect_ports(targ)) # simulation.setup_waveform(m, uut) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, resetn, m.make_reset(), period=100, polarity='low') init.add( Delay(10000000), Systask('finish'), ) # output source code if filename is not None: m.to_verilog(filename) # run simulation sim = simulation.Simulator(m, sim=simtype) rslt = sim.run(outputfile=outputfile) lines = rslt.splitlines() if simtype == 'verilator' and lines[-1].startswith('-'): rslt = '\n'.join(lines[:-1]) return rslt
def run(act_dtype=ng.int16, weight_dtype=ng.int16, bias_dtype=ng.int32, scale_dtype=ng.int16, with_batchnorm=False, disable_fusion=False, conv2d_par_ich=1, conv2d_par_och=1, conv2d_par_col=1, conv2d_par_row=1, conv2d_concur_och=None, conv2d_stationary='filter', pool_par=1, elem_par=1, chunk_size=64, axi_datawidth=32, silent=False, filename=None, simtype='iverilog', # simtype='verilator', # simtype=None, # no RTL simulation outputfile=None): # input mean and standard deviation cifar10_mean = np.array([0.4914, 0.4822, 0.4465]).astype(np.float32) cifar10_std = np.array([0.247, 0.243, 0.261]).astype(np.float32) act_shape = (1, 32, 32, 3) # pytorch model if with_batchnorm: model = torchvision.models.vgg11_bn(pretrained=False) else: model = torchvision.models.vgg11(pretrained=False) model.features[0].in_channels = act_shape[-1] model.avgpool = nn.Identity() #model.classifier[0] = nn.Linear(512, 4096) #model.classifier[6] = nn.Linear(4096, 10) model.classifier = nn.Sequential( nn.Linear(in_features=512, out_features=1024, bias=True), nn.ReLU(inplace=True), nn.Dropout(p=0.5), nn.Linear(in_features=1024, out_features=1024, bias=True), nn.ReLU(inplace=True), nn.Dropout(p=0.5), nn.Linear(in_features=1024, out_features=10, bias=True), ) # Pytorch to ONNX onnx_filename = 'vgg11.onnx' dummy_input = torch.randn(*act_shape).transpose(1, 3) input_names = ['act'] output_names = ['out'] model.eval() torch.onnx.export(model, dummy_input, onnx_filename, input_names=input_names, output_names=output_names) # -------------------- # (1) Represent a DNN model as a dataflow by NNgen operators # -------------------- # ONNX to NNgen dtypes = {} (outputs, placeholders, variables, constants, operators) = ng.from_onnx(onnx_filename, value_dtypes=dtypes, default_placeholder_dtype=act_dtype, default_variable_dtype=weight_dtype, default_constant_dtype=weight_dtype, default_operator_dtype=act_dtype, default_scale_dtype=scale_dtype, default_bias_dtype=bias_dtype, disable_fusion=disable_fusion) # -------------------- # (2) Assign quantized weights to the NNgen operators # -------------------- if act_dtype.width > 8: act_scale_factor = 128 else: act_scale_factor = int(round(2 ** (act_dtype.width - 1) * 0.5)) input_scale_factors = {'act': act_scale_factor} input_means = {'act': cifar10_mean * act_scale_factor} input_stds = {'act': cifar10_std * act_scale_factor} ng.quantize(outputs, input_scale_factors, input_means, input_stds) # -------------------- # (3) Assign hardware attributes # -------------------- for op in operators.values(): if isinstance(op, ng.conv2d): op.attribute(par_ich=conv2d_par_ich, par_och=conv2d_par_och, par_col=conv2d_par_col, par_row=conv2d_par_row, concur_och=conv2d_concur_och, stationary=conv2d_stationary) if isinstance(op, (ng.avg_pool, ng.max_pool, ng.avg_pool_serial, ng.max_pool_serial)): op.attribute(par=pool_par) if ng.is_elementwise_operator(op): op.attribute(par=elem_par) # -------------------- # (4) Verify the DNN model behavior by executing the NNgen dataflow as a software # -------------------- act = placeholders['act'] out = outputs['out'] # verification data # random data img = np.random.uniform(size=act.length).astype(np.float32).reshape(act.shape) img = img * 12.0 * cifar10_std + cifar10_mean # img = np.random.normal(size=act.length).astype(np.float32).reshape(act.shape) # img = img * cifar10_std + cifar10_mean # execution on pytorch model_input = img if act.perm is not None: model_input = np.transpose(model_input, act.reversed_perm) model.eval() model_out = model(torch.from_numpy(model_input)).detach().numpy() if act.perm is not None and len(model_out.shape) == len(act.shape): model_out = np.transpose(model_out, act.perm) scaled_model_out = model_out * out.scale_factor # software-based verification vact = img * act_scale_factor vact = np.clip(vact, -1.0 * (2 ** (act.dtype.width - 1) - 1), 1.0 * (2 ** (act.dtype.width - 1) - 1)) vact = np.round(vact).astype(np.int64) eval_outs = ng.eval([out], act=vact) vout = eval_outs[0] labels = ('plane', 'car', 'bird', 'cat', 'deer', 'dog', 'frog', 'horse', 'ship', 'truck') mout = scaled_model_out for bat in range(mout.shape[0]): for index, value in list(sorted(enumerate(mout[bat]), key=lambda x: x[1], reverse=True))[:10]: print("# mout: %s (%d) = %f" % (str(labels[index]), index, value)) for index, value in list(sorted(enumerate(vout[bat]), key=lambda x: x[1], reverse=True))[:10]: print("# vout: %s (%d) = %d" % (str(labels[index]), index, value)) # breakpoint() # -------------------- # (5) Convert the NNgen dataflow to a hardware description (Verilog HDL and IP-XACT) # -------------------- # to Veriloggen object # targ = ng.to_veriloggen([out], 'vgg11', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # to IP-XACT (the method returns Veriloggen object, as well as to_veriloggen) targ = ng.to_ipxact([out], 'onnx_vgg11', silent=silent, config={'maxi_datawidth': axi_datawidth}) # to Verilog HDL RTL (the method returns a source code text) # rtl = ng.to_verilog([out], 'vgg11', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # -------------------- # (6) Simulate the generated hardware by Veriloggen and Verilog simulator # -------------------- if simtype is None: sys.exit() # to memory image param_data = ng.export_ndarray([out], chunk_size) param_bytes = len(param_data) variable_addr = int(math.ceil((act.addr + act.memory_size) / chunk_size)) * chunk_size check_addr = int(math.ceil((variable_addr + param_bytes) / chunk_size)) * chunk_size tmp_addr = int(math.ceil((check_addr + out.memory_size) / chunk_size)) * chunk_size memimg_datawidth = 32 # mem = np.zeros([1024 * 1024 * 256 // (memimg_datawidth // 8)], dtype=np.int64) mem = np.zeros([1024 * 1024 * 1024 // (memimg_datawidth // 8)], dtype=np.int16) mem = mem + [100] # placeholder axi.set_memory(mem, vact, memimg_datawidth, act_dtype.width, act.addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), conv2d_par_ich)) # parameters (variable and constant) axi.set_memory(mem, param_data, memimg_datawidth, 8, variable_addr) # verification data axi.set_memory(mem, vout, memimg_datawidth, act_dtype.width, check_addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), conv2d_par_och)) # test controller m = Module('test') params = m.copy_params(targ) ports = m.copy_sim_ports(targ) clk = ports['CLK'] resetn = ports['RESETN'] rst = m.Wire('RST') rst.assign(Not(resetn)) # AXI memory model if outputfile is None: outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out' memimg_name = 'memimg_' + outputfile memory = axi.AxiMemoryModel(m, 'memory', clk, rst, datawidth=axi_datawidth, memimg=mem, memimg_name=memimg_name, memimg_datawidth=memimg_datawidth) memory.connect(ports, 'maxi') # AXI-Slave controller _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True) _saxi.connect(ports, 'saxi') # timer time_counter = m.Reg('time_counter', 32, initval=0) seq = Seq(m, 'seq', clk, rst) seq( time_counter.inc() ) def ctrl(): for i in range(100): pass ng.sim.set_global_addrs(_saxi, tmp_addr) start_time = time_counter.value ng.sim.start(_saxi) print('# start') ng.sim.wait(_saxi) end_time = time_counter.value print('# end') print('# execution cycles: %d' % (end_time - start_time)) # verify ok = True for bat in range(out.shape[0]): for x in range(out.shape[1]): orig = memory.read_word(bat * out.aligned_shape[1] + x, out.addr, act_dtype.width) check = memory.read_word(bat * out.aligned_shape[1] + x, check_addr, act_dtype.width) if vthread.verilog.NotEql(orig, check): print('NG (', bat, x, ') orig: ', orig, ' check: ', check) ok = False # else: # print('OK (', bat, x, # ') orig: ', orig, ' check: ', check) if ok: print('# verify: PASSED') else: print('# verify: FAILED') vthread.finish() th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl) fsm = th.start() uut = m.Instance(targ, 'uut', params=m.connect_params(targ), ports=m.connect_ports(targ)) # simulation.setup_waveform(m, uut) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, resetn, m.make_reset(), period=100, polarity='low') init.add( Delay(10000000), Systask('finish'), ) # output source code if filename is not None: m.to_verilog(filename) # run simulation sim = simulation.Simulator(m, sim=simtype) rslt = sim.run(outputfile=outputfile) lines = rslt.splitlines() if simtype == 'verilator' and lines[-1].startswith('-'): rslt = '\n'.join(lines[:-1]) return rslt
def run( act_dtype=ng.int8, weight_dtype=ng.int8, bias_dtype=ng.int32, scale_dtype=ng.int8, par_ich=2, par_och=2, chunk_size=64, axi_datawidth=32, silent=False, weight_filename='cnn.npy', verilog_filename=None, sim_filename=None, # simtype='iverilog', simtype='verilator', # simtype=None, # no RTL simulation ): # -------------------- # (1) Represent a DNN model as a dataflow by NNgen operators # -------------------- # input input_layer = ng.placeholder( dtype=act_dtype, shape=(1, 32, 32, 3), # N, H, W, C name='input_layer') # layer 0: conv2d (with bias and scale (= batchnorm)), relu, max_pool w0 = ng.variable( dtype=weight_dtype, shape=(64, 3, 3, 3), # Och, Ky, Kx, Ich name='w0') b0 = ng.variable(dtype=bias_dtype, shape=(w0.shape[0], ), name='b0') s0 = ng.variable(dtype=scale_dtype, shape=(w0.shape[0], ), name='s0') a0 = ng.conv2d(input_layer, w0, strides=(1, 1, 1, 1), bias=b0, scale=s0, act_func=ng.relu, dtype=act_dtype, sum_dtype=ng.int32) a0p = ng.max_pool_serial(a0, ksize=(1, 2, 2, 1), strides=(1, 2, 2, 1)) # layer 1: conv2d, relu, reshape w1 = ng.variable(weight_dtype, shape=(64, 3, 3, a0.shape[-1]), name='w1') b1 = ng.variable(bias_dtype, shape=(w1.shape[0], ), name='b1') s1 = ng.variable(scale_dtype, shape=(w1.shape[0], ), name='s1') a1 = ng.conv2d(a0p, w1, strides=(1, 1, 1, 1), bias=b1, scale=s1, act_func=ng.relu, dtype=act_dtype, sum_dtype=ng.int32) a1r = ng.reshape(a1, [1, -1]) # layer 2: full-connection, relu w2 = ng.variable(weight_dtype, shape=(256, a1r.shape[-1]), name='w2') b2 = ng.variable(bias_dtype, shape=(w2.shape[0], ), name='b2') s2 = ng.variable(scale_dtype, shape=(w2.shape[0], ), name='s2') a2 = ng.matmul(a1r, w2, bias=b2, scale=s2, transposed_b=True, act_func=ng.relu, dtype=act_dtype, sum_dtype=ng.int32) # layer 3: full-connection, relu w3 = ng.variable(weight_dtype, shape=(10, a2.shape[-1]), name='w3') b3 = ng.variable(bias_dtype, shape=(w3.shape[0], ), name='b3') s3 = ng.variable(scale_dtype, shape=(w3.shape[0], ), name='s3') # output output_layer = ng.matmul(a2, w3, bias=b3, scale=s3, transposed_b=True, name='output_layer', dtype=act_dtype, sum_dtype=ng.int32) # -------------------- # (2) Assign weights to the NNgen operators # -------------------- # In this example, random floating-point values are assigned. # In a real case, you should assign actual weight values # obtianed by a training on DNN framework. # If you don't you NNgen's quantizer, you can assign integer weights to each tensor. w0_value = np.random.normal(size=w0.length).reshape(w0.shape) w0_value = np.clip(w0_value, -3.0, 3.0) w0.set_value(w0_value) b0_value = np.random.normal(size=b0.length).reshape(b0.shape) b0_value = np.clip(b0_value, -3.0, 3.0) b0.set_value(b0_value) s0_value = np.ones(s0.shape) s0.set_value(s0_value) w1_value = np.random.normal(size=w1.length).reshape(w1.shape) w1_value = np.clip(w1_value, -3.0, 3.0) w1.set_value(w1_value) b1_value = np.random.normal(size=b1.length).reshape(b1.shape) b1_value = np.clip(b1_value, -3.0, 3.0) b1.set_value(b1_value) s1_value = np.ones(s1.shape) s1.set_value(s1_value) w2_value = np.random.normal(size=w2.length).reshape(w2.shape) w2_value = np.clip(w2_value, -3.0, 3.0) w2.set_value(w2_value) b2_value = np.random.normal(size=b2.length).reshape(b2.shape) b2_value = np.clip(b2_value, -3.0, 3.0) b2.set_value(b2_value) s2_value = np.ones(s2.shape) s2.set_value(s2_value) w3_value = np.random.normal(size=w3.length).reshape(w3.shape) w3_value = np.clip(w3_value, -3.0, 3.0) w3.set_value(w3_value) b3_value = np.random.normal(size=b3.length).reshape(b3.shape) b3_value = np.clip(b3_value, -3.0, 3.0) b3.set_value(b3_value) s3_value = np.ones(s3.shape) s3.set_value(s3_value) # Quantizing the floating-point weights by the NNgen quantizer. # Alternatively, you can assign integer weights by yourself to each tensor. imagenet_mean = np.array([0.485, 0.456, 0.406]).astype(np.float32) imagenet_std = np.array([0.229, 0.224, 0.225]).astype(np.float32) if act_dtype.width > 8: act_scale_factor = 128 else: act_scale_factor = int(round(2**(act_dtype.width - 1) * 0.5)) input_scale_factors = {'input_layer': act_scale_factor} input_means = {'input_layer': imagenet_mean * act_scale_factor} input_stds = {'input_layer': imagenet_std * act_scale_factor} ng.quantize([output_layer], input_scale_factors, input_means, input_stds) # -------------------- # (3) Assign hardware attributes # -------------------- # conv2d, matmul # par_ich: parallelism in input-channel # par_och: parallelism in output-channel # par_col: parallelism in pixel column # par_row: parallelism in pixel row a0.attribute(par_ich=par_ich, par_och=par_och) a1.attribute(par_ich=par_ich, par_och=par_och) a2.attribute(par_ich=par_ich, par_och=par_och) output_layer.attribute(par_ich=par_ich, par_och=par_och) # cshamt_out: right shift amount after applying bias/scale # If you assign integer weights by yourself to each tensor, # cshamt (constant shift amount) must be assigned to each operator. # a0.attribute(cshamt_out=weight_dtype.width + 1) # a1.attribute(cshamt_out=weight_dtype.width + 1) # a2.attribute(cshamt_out=weight_dtype.width + 1) # output_layer.attribute(cshamt_out=weight_dtype.width + 1) # max_pool # par: parallelism in in/out channel par = par_och a0p.attribute(par=par) # -------------------- # (4) Verify the DNN model behavior by executing the NNgen dataflow as a software # -------------------- # In this example, random integer values are assigned. # In real case, you should assign actual integer activation values, such as an image. input_layer_value = np.random.normal(size=input_layer.length).reshape( input_layer.shape) input_layer_value = input_layer_value * imagenet_std + imagenet_mean input_layer_value = np.clip(input_layer_value, -5.0, 5.0) input_layer_value = input_layer_value * act_scale_factor input_layer_value = np.clip(input_layer_value, -1 * 2**(act_dtype.width - 1) - 1, 2**(act_dtype.width - 1)) input_layer_value = np.round(input_layer_value).astype(np.int64) eval_outs = ng.eval([output_layer], input_layer=input_layer_value) output_layer_value = eval_outs[0] # print(output_layer_value) # breakpoint() # -------------------- # (5) Convert the NNgen dataflow to a hardware description (Verilog HDL and IP-XACT) # -------------------- # to Veriloggen object # targ = ng.to_veriloggen([output_layer], 'cnn', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # to IP-XACT (the method returns Veriloggen object, as well as to_veriloggen) targ = ng.to_ipxact([output_layer], 'cnn', silent=silent, config={'maxi_datawidth': axi_datawidth}) # to Verilog HDL RTL (the method returns a source code text) # rtl = ng.to_verilog([output_layer], 'cnn', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # -------------------- # (6) Save the quantized weights # -------------------- # convert weight values to a memory image: # on a real FPGA platform, this image will be used as a part of the model definition. param_filename = 'hello_nngen.npy' chunk_size = 64 param_data = ng.export_ndarray([output_layer], chunk_size) np.save(weight_filename, param_data) # -------------------- # (7) Simulate the generated hardware by Veriloggen and Verilog simulator # -------------------- if simtype is None: sys.exit() param_bytes = len(param_data) variable_addr = int( math.ceil((input_layer.addr + input_layer.memory_size) / chunk_size)) * chunk_size check_addr = int(math.ceil( (variable_addr + param_bytes) / chunk_size)) * chunk_size tmp_addr = int( math.ceil( (check_addr + output_layer.memory_size) / chunk_size)) * chunk_size memimg_datawidth = 32 mem = np.zeros([1024 * 1024 * 256 // (memimg_datawidth // 8)], dtype=np.int64) mem = mem + [100] # placeholder axi.set_memory( mem, input_layer_value, memimg_datawidth, act_dtype.width, input_layer.addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), par_ich)) # parameters (variable and constant) axi.set_memory(mem, param_data, memimg_datawidth, 8, variable_addr) # verification data axi.set_memory( mem, output_layer_value, memimg_datawidth, act_dtype.width, check_addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), par_och)) # test controller m = Module('test') params = m.copy_params(targ) ports = m.copy_sim_ports(targ) clk = ports['CLK'] resetn = ports['RESETN'] rst = m.Wire('RST') rst.assign(Not(resetn)) # AXI memory model if sim_filename is None: sim_filename = os.path.splitext(os.path.basename(__file__))[0] + '.out' memimg_name = 'memimg_' + sim_filename memory = axi.AxiMemoryModel(m, 'memory', clk, rst, datawidth=axi_datawidth, memimg=mem, memimg_name=memimg_name, memimg_datawidth=memimg_datawidth) memory.connect(ports, 'maxi') # AXI-Slave controller _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True) _saxi.connect(ports, 'saxi') # timer time_counter = m.Reg('time_counter', 32, initval=0) seq = Seq(m, 'seq', clk, rst) seq(time_counter.inc()) def ctrl(): for i in range(100): pass ng.sim.set_global_addrs(_saxi, tmp_addr) start_time = time_counter.value ng.sim.start(_saxi) print('# start') ng.sim.wait(_saxi) end_time = time_counter.value print('# end') print('# execution cycles: %d' % (end_time - start_time)) # verify ok = True for bat in range(output_layer.shape[0]): for x in range(output_layer.shape[1]): orig = memory.read_word( bat * output_layer.aligned_shape[1] + x, output_layer.addr, act_dtype.width) check = memory.read_word( bat * output_layer.aligned_shape[1] + x, check_addr, act_dtype.width) if vthread.verilog.NotEql(orig, check): print('NG (', bat, x, ') orig: ', orig, ' check: ', check) ok = False else: print('OK (', bat, x, ') orig: ', orig, ' check: ', check) if ok: print('# verify: PASSED') else: print('# verify: FAILED') vthread.finish() th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl) fsm = th.start() uut = m.Instance(targ, 'uut', params=m.connect_params(targ), ports=m.connect_ports(targ)) # simulation.setup_waveform(m, uut) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, resetn, m.make_reset(), period=100, polarity='low') init.add( Delay(10000000), Systask('finish'), ) # output source code if verilog_filename is not None: m.to_verilog(verilog_filename) # run simulation sim = simulation.Simulator(m, sim=simtype) rslt = sim.run(outputfile=sim_filename) lines = rslt.splitlines() if simtype == 'verilator' and lines[-1].startswith('-'): rslt = '\n'.join(lines[:-1]) return rslt
def run(a_shape=(15, 15), b_shape=(15, 15), a_dtype=ng.int32, b_dtype=ng.int32, c_dtype=ng.int32, par=1, axi_datawidth=32, silent=False, filename=None, simtype='iverilog', outputfile=None): # create target hardware a = ng.placeholder(a_dtype, shape=a_shape, name='a') b = ng.placeholder(b_dtype, shape=b_shape, name='b') c = ng.add(a, b, dtype=c_dtype, par=par, name='c') targ = ng.to_ipxact([c], 'matrix_add_ipxact', silent=silent, config={'maxi_datawidth': axi_datawidth}) # verification data va = np.arange(a.length, dtype=np.int64).reshape(a.shape) % [5] vb = (np.arange(b.length, dtype=np.int64).reshape(b.shape) + [100]) % [6] eval_outs = ng.eval([c], a=va, b=vb) vc = eval_outs[0] # to memory image size_max = int( math.ceil( max(a.memory_size, b.memory_size, c.memory_size) / 4096)) * 4096 check_addr = max(a.addr, b.addr, c.addr) + size_max size_check = size_max tmp_addr = check_addr + size_check memimg_datawidth = 32 mem = np.zeros([1024 * 1024 * 8 // (memimg_datawidth // 8)], dtype=np.int64) mem = mem + [100] axi.set_memory(mem, va, memimg_datawidth, a_dtype.width, a.addr, max(int(math.ceil(axi_datawidth / a_dtype.width)), par)) axi.set_memory(mem, vb, memimg_datawidth, b_dtype.width, b.addr, max(int(math.ceil(axi_datawidth / b_dtype.width)), par)) axi.set_memory(mem, vc, memimg_datawidth, c_dtype.width, check_addr, max(int(math.ceil(axi_datawidth / c_dtype.width)), par)) # test controller m = Module('test') params = m.copy_params(targ) ports = m.copy_sim_ports(targ) clk = ports['CLK'] resetn = ports['RESETN'] rst = m.Wire('RST') rst.assign(Not(resetn)) # AXI memory model if outputfile is None: outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out' memimg_name = 'memimg_' + outputfile memory = axi.AxiMemoryModel(m, 'memory', clk, rst, datawidth=axi_datawidth, memimg=mem, memimg_name=memimg_name, memimg_datawidth=memimg_datawidth) memory.connect(ports, 'maxi') # AXI-Slave controller _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True) _saxi.connect(ports, 'saxi') # timer time_counter = m.Reg('time_counter', 32, initval=0) seq = Seq(m, 'seq', clk, rst) seq(time_counter.inc()) num_rep = functools.reduce(lambda x, y: x * y, c.shape[:-1], 1) def ctrl(): for i in range(100): pass ng.sim.set_global_addrs(_saxi, tmp_addr) start_time = time_counter.value ng.sim.start(_saxi) print('# start') ng.sim.wait(_saxi) end_time = time_counter.value print('# end') print('# execution cycles: %d' % (end_time - start_time)) # verify ok = True for i in range(num_rep): for j in range(c.shape[-1]): orig = memory.read_word(i * c.aligned_shape[-1] + j, c.addr, c_dtype.width) check = memory.read_word(i * c.aligned_shape[-1] + j, check_addr, c_dtype.width) if vthread.verilog.NotEql(orig, check): print('NG', i, j, orig, check) ok = False # else: # print('OK', i, j, orig, check) if ok: print('# verify: PASSED') else: print('# verify: FAILED') vthread.finish() th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl) fsm = th.start() uut = m.Instance(targ, 'uut', params=m.connect_params(targ), ports=m.connect_ports(targ)) # simulation.setup_waveform(m, uut) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, resetn, m.make_reset(), period=100, polarity='low') init.add( Delay(1000000), Systask('finish'), ) # output source code if filename is not None: m.to_verilog(filename) # run simulation sim = simulation.Simulator(m, sim=simtype) rslt = sim.run(outputfile=outputfile) lines = rslt.splitlines() if simtype == 'verilator' and lines[-1].startswith('-'): rslt = '\n'.join(lines[:-1]) return rslt
scale_ram_size=1024, out_ram_size=4096) # --- Generate from conv2d_attribute_ram.j2 --- L045_layer19_conv_cv_cbs.attribute(input_ram_size=1024, filter_ram_size=1024, bias_ram_size=1024, scale_ram_size=1024, out_ram_size=4096) # --- Generate from conv2d_attribute_ram.j2 --- L051_layer22_conv_cv_cbs.attribute(input_ram_size=1024, filter_ram_size=1024, bias_ram_size=1024, scale_ram_size=1024, out_ram_size=4096) # --- Generate from conv2d_attribute_ram.j2 --- L055_c_layer23_conv_cv.attribute(input_ram_size=1024, filter_ram_size=1024, bias_ram_size=1024, scale_ram_size=1024, out_ram_size=4096) _outputs = get_outputs(operators) m = ng.to_ipxact(_outputs, IPNAME, config=user_config) post_process({'X_FORCE_DSP': True}, IPNAME) #print(placeholders) #print(variables) #print(operators)
def run( act_dtype=ng.int16, weight_dtype=ng.int8, bias_dtype=ng.int32, scale_dtype=ng.int8, disable_fusion=False, conv2d_par_ich=1, conv2d_par_och=1, conv2d_par_col=1, conv2d_par_row=1, conv2d_concur_och=None, conv2d_stationary='filter', pool_par=1, elem_par=1, chunk_size=64, axi_datawidth=32, silent=False, onnx_filename='yolov3-tiny.onnx', weight_filename='yolov3-tiny.npy', verilog_filename=None, sim_filename=None, # simtype=None, # no RTL simulation # simtype='iverilog', simtype='verilator', cfg_filename='yolov3-tiny.cfg', weights_filename='yolov3-tiny.weights', model_path='yolov3'): # input mean and standard deviation imagenet_mean = np.array([0.485, 0.456, 0.406]).astype(np.float32) imagenet_std = np.array([0.229, 0.224, 0.225]).astype(np.float32) img_size = (416, 416) act_shape = (1, img_size[0], img_size[1], 3) # pytorch model model_url = "https://github.com/ultralytics/yolov3" if not os.path.isdir(model_path): raise FileNotFoundError( "Download the YOLOv3 model using Pytorch, such as " "'%s'. Then extract it, and rename it as '%s'" % (model_url, model_path)) # Darknet model configuration and pretrained weights cfg_url = "https://github.com/pjreddie/darknet/blob/master/cfg/yolov3-tiny.cfg" if not os.path.isfile(cfg_filename): urllib.request.urlretrieve(cfg_url, cfg_filename) weights_url = "https://pjreddie.com/media/files/yolov3-tiny.weights" if not os.path.isfile(weights_filename): urllib.request.urlretrieve(weights_url, weights_filename) sys.path.insert(0, model_path) import models models.ONNX_EXPORT = True model = models.Darknet(cfg_filename, img_size).to('cpu') models.load_darknet_weights(model, weights_filename) # Pytorch to ONNX dummy_input = torch.randn(*act_shape).transpose(1, 3) input_names = ['act'] output_names = ['scores', 'boxes'] model.eval() torch.onnx.export(model, dummy_input, onnx_filename, input_names=input_names, output_names=output_names) # -------------------- # (1) Represent a DNN model as a dataflow by NNgen operators # -------------------- # ONNX to NNgen dtypes = {} shapes = {} (outputs, placeholders, variables, constants, operators) = ng.from_onnx(onnx_filename, value_dtypes=dtypes, value_shapes=shapes, default_placeholder_dtype=act_dtype, default_variable_dtype=weight_dtype, default_constant_dtype=weight_dtype, default_operator_dtype=act_dtype, default_scale_dtype=scale_dtype, default_bias_dtype=bias_dtype, disable_fusion=disable_fusion, verbose=False) # -------------------- # (2) Assign quantized weights to the NNgen operators # -------------------- if act_dtype.width > 8: act_scale_factor = 128 else: act_scale_factor = int(round(2**(act_dtype.width - 1) * 0.5)) input_scale_factors = {'act': act_scale_factor} input_means = {'act': imagenet_mean * act_scale_factor} input_stds = {'act': imagenet_std * act_scale_factor} ng.quantize(outputs, input_scale_factors, input_means, input_stds) # -------------------- # (3) Assign hardware attributes # -------------------- for op in operators.values(): if isinstance(op, ng.conv2d): op.attribute(par_ich=conv2d_par_ich, par_och=conv2d_par_och, par_col=conv2d_par_col, par_row=conv2d_par_row, concur_och=conv2d_concur_och, stationary=conv2d_stationary) if isinstance(op, (ng.avg_pool, ng.max_pool, ng.avg_pool_serial, ng.max_pool_serial)): op.attribute(par=pool_par) if ng.is_elementwise_operator(op): op.attribute(par=elem_par) # -------------------- # (4) Verify the DNN model behavior by executing the NNgen dataflow as a software # -------------------- act = placeholders['act'] outs = (outputs['scores'], outputs['boxes']) # verification data img = np.array(PIL.Image.open('car416x416.png').convert('RGB')).astype( np.float32) img = img.reshape([1] + list(img.shape)) img = img / 255 img = (img - imagenet_mean) / imagenet_std # execution on pytorch model_input = img if act.perm is not None: model_input = np.transpose(model_input, act.reversed_perm) model.eval() model_rslts = model(torch.from_numpy(model_input)) model_outs = [rslt.detach().numpy() for rslt in model_rslts] model_outs = [(np.transpose(model_out, act.perm) if act.perm is not None and len(model_out.shape) == len(act.shape) else model_out) for model_out in model_outs] scaled_model_outs = [ model_out * out.scale_factor for model_out, out in zip(model_outs, outs) ] # software-based verification vact = img * act_scale_factor vact = np.clip(vact, -1.0 * (2**(act.dtype.width - 1) - 1), 1.0 * (2**(act.dtype.width - 1) - 1)) vact = np.round(vact).astype(np.int64) # compare outputs of hidden layers leaky_relu_ops = [ v for k, v in operators.items() if (isinstance(v, ng.conv2d) and isinstance(v.act_func, ng.leaky_relu_base)) ] leaky_relu_ops = list(sorted(set(leaky_relu_ops), key=leaky_relu_ops.index)) conv2d_ops = [ v for k, v in operators.items() if (isinstance(v, ng.conv2d) and v.act_func is None) ] conv2d_ops = list(sorted(set(conv2d_ops), key=conv2d_ops.index)) # only 1st output sub_ops = leaky_relu_ops[:9] + conv2d_ops[:1] sub_outs = ng.eval(sub_ops, act=vact) sub_outs = [sub_out.transpose([0, 3, 1, 2]) for sub_out in sub_outs] sub_scale_factors = [sub_op.scale_factor for sub_op in sub_ops] model.eval() mouts = [] # all Conv2d-LeakyReLU layers before YOLOLayer mouts.append( nn.Sequential(model.module_list[0])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:3])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:5])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:7])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:9])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:11])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:13])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:14])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:15])( torch.from_numpy(model_input)).detach().numpy()) mouts.append( nn.Sequential(*model.module_list[0:16])( torch.from_numpy(model_input)).detach().numpy()) scaled_mouts = [ mout * scale_factor for mout, scale_factor in zip(mouts, sub_scale_factors) ] sub_mean_square_errors = [ np.sum((sub_out - mout)**2) / sub_out.size for mout, sub_out in zip(scaled_mouts, sub_outs) ] sub_corrcoefs = [ np.corrcoef(mout.reshape([-1]), sub_out.reshape([-1])) for mout, sub_out in zip(mouts, sub_outs) ] # compare prediction results vouts = ng.eval(outs, act=vact) mean_square_errors = [ np.sum((vout - scaled_model_out)**2) / vout.size for vout, scaled_model_out in zip(vouts, scaled_model_outs) ] corrcoefs = [ np.corrcoef(model_out.reshape([-1]), vout.reshape([-1])) for model_out, vout in zip(model_outs, vouts) ] # breakpoint() # -------------------- # (5) Convert the NNgen dataflow to a hardware description (Verilog HDL and IP-XACT) # -------------------- # to Veriloggen object # targ = ng.to_veriloggen(outs, 'yolov3tiny', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # to IP-XACT (the method returns Veriloggen object, as well as to_veriloggen) targ = ng.to_ipxact(outs, 'yolov3tiny', silent=silent, config={'maxi_datawidth': axi_datawidth}) # to Verilog HDL RTL (the method returns a source code text) # rtl = ng.to_verilog(outs, 'yolov3tiny', silent=silent, # config={'maxi_datawidth': axi_datawidth}) # -------------------- # (6) Save the quantized weights # -------------------- param_data = ng.export_ndarray(outs, chunk_size) param_bytes = len(param_data) np.save(weight_filename, param_data) # -------------------- # (7) Simulate the generated hardware by Veriloggen and Verilog simulator # -------------------- if simtype is None: sys.exit() variable_addr = int(math.ceil( (act.addr + act.memory_size) / chunk_size)) * chunk_size check0_addr = int(math.ceil( (variable_addr + param_bytes) / chunk_size)) * chunk_size check1_addr = int( math.ceil( (check0_addr + outs[0].memory_size) / chunk_size)) * chunk_size tmp_addr = int(math.ceil( (check1_addr + outs[1].memory_size) / chunk_size)) * chunk_size memimg_datawidth = 32 # mem = np.zeros([1024 * 1024 * 256 // (memimg_datawidth // 8)], dtype=np.int64) mem = np.zeros([1024 * 1024 * 256 // (memimg_datawidth // 8)], dtype=np.int16) mem = mem + [100] # placeholder axi.set_memory( mem, vact, memimg_datawidth, act_dtype.width, act.addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), conv2d_par_ich)) # parameters (variable and constant) axi.set_memory(mem, param_data, memimg_datawidth, 8, variable_addr) # verification data axi.set_memory( mem, vouts[0], memimg_datawidth, act_dtype.width, check0_addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), conv2d_par_och)) axi.set_memory( mem, vouts[1], memimg_datawidth, act_dtype.width, check1_addr, max(int(math.ceil(axi_datawidth / act_dtype.width)), conv2d_par_och)) # test controller m = Module('test') params = m.copy_params(targ) ports = m.copy_sim_ports(targ) clk = ports['CLK'] resetn = ports['RESETN'] rst = m.Wire('RST') rst.assign(Not(resetn)) # AXI memory model if sim_filename is None: sim_filename = os.path.splitext(os.path.basename(__file__))[0] + '.out' memimg_name = 'memimg_' + sim_filename memory = axi.AxiMemoryModel(m, 'memory', clk, rst, datawidth=axi_datawidth, memimg=mem, memimg_name=memimg_name, memimg_datawidth=memimg_datawidth) memory.connect(ports, 'maxi') # AXI-Slave controller _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True) _saxi.connect(ports, 'saxi') # timer time_counter = m.Reg('time_counter', 32, initval=0) seq = Seq(m, 'seq', clk, rst) seq(time_counter.inc()) def ctrl(): for i in range(100): pass ng.sim.set_global_addrs(_saxi, tmp_addr) start_time = time_counter.value ng.sim.start(_saxi) print('# start') ng.sim.wait(_saxi) end_time = time_counter.value print('# end') print('# execution cycles: %d' % (end_time - start_time)) # verify ok = True for bat in range(outs[0].shape[0]): for x in range(outs[0].shape[1]): orig = memory.read_word(bat * outs[0].aligned_shape[1] + x, outs[0].addr, act_dtype.width) check = memory.read_word(bat * outs[0].aligned_shape[1] + x, check0_addr, act_dtype.width) if vthread.verilog.NotEql(orig, check): print('NG (', bat, x, ') orig: ', orig, ' check: ', check) ok = False # else: # print('OK (', bat, x, # ') orig: ', orig, ' check: ', check) for bat in range(outs[1].shape[0]): for x in range(outs[1].shape[1]): orig = memory.read_word(bat * outs[1].aligned_shape[1] + x, outs[1].addr, act_dtype.width) check = memory.read_word(bat * outs[1].aligned_shape[1] + x, check1_addr, act_dtype.width) if vthread.verilog.NotEql(orig, check): print('NG (', bat, x, ') orig: ', orig, ' check: ', check) ok = False # else: # print('OK (', bat, x, # ') orig: ', orig, ' check: ', check) if ok: print('# verify: PASSED') else: print('# verify: FAILED') vthread.finish() th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl) fsm = th.start() uut = m.Instance(targ, 'uut', params=m.connect_params(targ), ports=m.connect_ports(targ)) # simulation.setup_waveform(m, uut) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, resetn, m.make_reset(), period=100, polarity='low') init.add( Delay(10000000), Systask('finish'), ) # output source code if verilog_filename is not None: m.to_verilog(verilog_filename) # run simulation sim = simulation.Simulator(m, sim=simtype) rslt = sim.run(outputfile=sim_filename) lines = rslt.splitlines() if simtype == 'verilator' and lines[-1].startswith('-'): rslt = '\n'.join(lines[:-1]) return rslt