def test_full_bus_with_integration(self):
sm = som.SOM()
sm.initialize_root()
root = sm.get_root()
peripheral = sm.insert_bus()
peripheral.set_name("peripheral")
memory = sm.insert_bus()
memory.set_name("memory")
d1 = sdbc.create_device_record(name = "device 1", size = 0x100)
d2 = sdbc.create_device_record(name = "device 2", size = 0x100)
m1 = sdbc.create_device_record(name = "memory 1", size = 0x10000)
m2 = sdbc.create_device_record(name = "memory 2", size = 0x20000)
intr = sdbc.create_integration_record("Integration Data",
vendor_id = 0x800BEAF15DEADC03,
device_id = 0x00000000)
peripheral.set_child_spacing(0x0100000000)
sm.insert_component(peripheral, intr)
sm.insert_component(peripheral, d1)
sm.insert_component(peripheral, d2)
sm.insert_component(memory, m1)
sm.insert_component(memory, m2)
rom = generate_rom_image(sm)
rom_in = sdbc.convert_rom_to_32bit_buffer(rom)
#rom_in = ROM2
#print_sdb_rom(rom_in)
sm = parse_rom_image(rom_in)
rom_out = generate_rom_image(sm)
rom_out = sdbc.convert_rom_to_32bit_buffer(rom_out)
#print_sdb_rom(rom_out)
#compare_roms(rom_in, rom_out)
self.assertEqual(rom_in, rom_out)
def test_full_bus_with_integration(self):
sm = som.SOM()
sm.initialize_root()
root = sm.get_root()
peripheral = sm.insert_bus()
peripheral.set_name("peripheral")
memory = sm.insert_bus()
memory.set_name("memory")
d1 = sdbc.create_device_record(name="device 1", size=0x100)
d2 = sdbc.create_device_record(name="device 2", size=0x100)
m1 = sdbc.create_device_record(name="memory 1", size=0x10000)
m2 = sdbc.create_device_record(name="memory 2", size=0x20000)
intr = sdbc.create_integration_record("Integration Data",
vendor_id=0x800BEAF15DEADC03,
device_id=0x00000000)
peripheral.set_child_spacing(0x0100000000)
sm.insert_component(peripheral, intr)
sm.insert_component(peripheral, d1)
sm.insert_component(peripheral, d2)
sm.insert_component(memory, m1)
sm.insert_component(memory, m2)
rom = generate_rom_image(sm)
rom_in = sdbc.convert_rom_to_32bit_buffer(rom)
#rom_in = ROM2
#print_sdb_rom(rom_in)
sm = parse_rom_image(rom_in)
rom_out = generate_rom_image(sm)
rom_out = sdbc.convert_rom_to_32bit_buffer(rom_out)
#print_sdb_rom(rom_out)
#compare_roms(rom_in, rom_out)
self.assertEqual(rom_in, rom_out)
def print_sdb(rom):
rom = sdbc.convert_rom_to_32bit_buffer(rom)
rom = rom.splitlines()
print "ROM"
for i in range (0, len(rom), 4):
if (i % 16 == 0):
magic = "0x%s" % (rom[i].lower())
last_val = int(rom[i + 15], 16) & 0xFF
print ""
if (magic == hex(sdbc.SDB_INTERCONNECT_MAGIC) and last_val == 0):
print "Interconnect"
elif last_val == 0x01:
print "Device"
elif last_val == 0x02:
print "Bridge"
elif last_val == 0x80:
print "Integration"
elif last_val == 0x81:
print "URL"
elif last_val == 0x82:
print "Synthesis"
elif last_val == 0xFF:
print "Empty"
else:
print "???"
print "%s %s : %s %s" % (rom[i], rom[i + 1], rom[i + 2], rom[i + 3])
def print_sdb(rom):
rom = sdbc.convert_rom_to_32bit_buffer(rom)
rom = rom.splitlines()
print "ROM"
for i in range(0, len(rom), 4):
if (i % 16 == 0):
magic = "0x%s" % (rom[i].lower())
last_val = int(rom[i + 15], 16) & 0xFF
print ""
if (magic == hex(sdbc.SDB_INTERCONNECT_MAGIC) and last_val == 0):
print "Interconnect"
elif last_val == 0x01:
print "Device"
elif last_val == 0x02:
print "Bridge"
elif last_val == 0x80:
print "Integration"
elif last_val == 0x81:
print "URL"
elif last_val == 0x82:
print "Synthesis"
elif last_val == 0xFF:
print "Empty"
else:
print "???"
print "%s %s : %s %s" % (rom[i], rom[i + 1], rom[i + 2], rom[i + 3])
def test_generate_one_sub_bus_with_url(self):
rom_in = ROMD
#print_sdb(rom)
sm = parse_rom_image(rom_in)
rom_out = generate_rom_image(sm)
rom_out = sdbc.convert_rom_to_32bit_buffer(rom_out)
print_sdb_rom(rom_out)
#compare_roms(rom_in, rom_out)
self.assertEqual(rom_in, rom_out)
def test_generate_one_sub_bus_with_url(self):
rom_in = ROMD
#print_sdb(rom)
sm = parse_rom_image(rom_in)
rom_out = generate_rom_image(sm)
rom_out = sdbc.convert_rom_to_32bit_buffer(rom_out)
print_sdb_rom(rom_out)
#compare_roms(rom_in, rom_out)
self.assertEqual(rom_in, rom_out)
def test_generate_one_sub_bus_with_url(self):
sm = som.SOM()
sm.initialize_root()
root = sm.get_root()
peripheral = sm.insert_bus()
peripheral.set_name("peripheral")
memory = sm.insert_bus()
memory.set_name("memory")
d1 = sdbc.create_device_record(name="device 1", size=0x100)
d2 = sdbc.create_device_record(name="device 2", size=0x100)
m1 = sdbc.create_device_record(name="memory 1", size=0x10000)
m2 = sdbc.create_device_record(name="memory 2", size=0x20000)
intr = sdbc.create_integration_record("Integration Data",
vendor_id=0x800BEAF15DEADC03,
device_id=0x00000000)
url = sdbc.create_repo_url_record("http://www.geocities.com")
synthesis = sdbc.create_synthesis_record("Synthesis Name", 123,
"cool tool", 1.0, "jeff")
sm.insert_component(root, url)
sm.insert_component(root, synthesis)
peripheral.set_child_spacing(0x0100000000)
sm.insert_component(peripheral, intr)
sm.insert_component(peripheral, d1)
sm.insert_component(peripheral, d2)
sm.insert_component(memory, m1)
sm.insert_component(memory, m2)
rom = generate_rom_image(sm)
rom_in = sdbc.convert_rom_to_32bit_buffer(rom)
#print_sdb(rom)
sm = parse_rom_image(rom_in)
rom_out = generate_rom_image(sm)
rom_out = sdbc.convert_rom_to_32bit_buffer(rom_out)
#print_sdb_rom(rom_out)
#compare_roms(rom_in, rom_out)
self.assertEqual(rom_in, rom_out)
def test_generate_one_sub_bus_with_url(self):
sm = som.SOM()
sm.initialize_root()
root = sm.get_root()
peripheral = sm.insert_bus()
peripheral.set_name("peripheral")
memory = sm.insert_bus()
memory.set_name("memory")
d1 = sdbc.create_device_record(name = "device 1", size = 0x100)
d2 = sdbc.create_device_record(name = "device 2", size = 0x100)
m1 = sdbc.create_device_record(name = "memory 1", size = 0x10000)
m2 = sdbc.create_device_record(name = "memory 2", size = 0x20000)
intr = sdbc.create_integration_record("Integration Data",
vendor_id = 0x800BEAF15DEADC03,
device_id = 0x00000000)
url = sdbc.create_repo_url_record("http://www.geocities.com")
synthesis = sdbc.create_synthesis_record("Synthesis Name", 123, "cool tool", 1.0, "jeff")
sm.insert_component(root, url)
sm.insert_component(root, synthesis)
peripheral.set_child_spacing(0x0100000000)
sm.insert_component(peripheral, intr)
sm.insert_component(peripheral, d1)
sm.insert_component(peripheral, d2)
sm.insert_component(memory, m1)
sm.insert_component(memory, m2)
rom = generate_rom_image(sm)
rom_in = sdbc.convert_rom_to_32bit_buffer(rom)
#print_sdb(rom)
sm = parse_rom_image(rom_in)
rom_out = generate_rom_image(sm)
rom_out = sdbc.convert_rom_to_32bit_buffer(rom_out)
#print_sdb_rom(rom_out)
#compare_roms(rom_in, rom_out)
self.assertEqual(rom_in, rom_out)
def setup_som_raw(self):
rom = self.platform.read_sdb()
self.sdb_rom = convert_rom_to_32bit_buffer(self.platform.read_sdb())
rom = self.sdb_rom.splitlines()
#print "rom: %s" % rom
data = []
component_data = None
name = None
address = "0x%04X" % 0x00
buf = []
for i in range (0, len(rom), 4):
if (i % 16 == 0):
if name is not None:
data.append([address, name, buf])
address = "0x%04X" % (i / 2)
buf = []
#print "rom data: %s" % str(rom[i])
magic = "0x%s" % (rom[i].lower())
last_val = int(rom[i + 15], 16) & 0xFF
#print "magic: %s" % magic
magic = int(rom[i], 16)
#if (magic == hex(SDB_INTERCONNECT_MAGIC) and (last_val == 0)):
if (magic == SDB_INTERCONNECT_MAGIC and (last_val == 0)):
name = "Interconnect"
elif last_val == 0x01:
name = "Device"
elif last_val == 0x02:
name = "Bridge"
elif last_val == 0x80:
name = "Integration"
elif last_val == 0x81:
name = "URL"
elif last_val == 0x82:
name = "Synthesis"
elif last_val == 0xFF:
name = "Empty"
else:
name = "???"
buf.append("%s %s : %s %s" % (rom[i], rom[i + 1], rom[i + 2], rom[i + 3]))
data.append([address, name, buf])
#print "sdb: %s" % str(data)
for raw_sdb_component in data:
self.v.add_sdb_raw_entry(data.index(raw_sdb_component), raw_sdb_component[0], raw_sdb_component[1], raw_sdb_component[2])
def gen_script(self, tags = {}, buf = "", user_paths = [], debug = False):
rom = self.gen_rom(tags, buf, user_paths, debug)
buf = sdbc.convert_rom_to_32bit_buffer(rom)
return buf
def write_to_file(rom, filename):
rom = sdbc.convert_rom_to_32bit_buffer(rom)
f = open(filename, 'w')
f.write(rom)
f.close()
def write_to_file(rom, filename):
rom = sdbc.convert_rom_to_32bit_buffer(rom)
f = open(filename, 'w')
f.write(rom)
f.close()
def gen_script(self, tags={}, buf="", user_paths=[], debug=False):
rom = self.gen_rom(tags, buf, user_paths, debug)
buf = sdbc.convert_rom_to_32bit_buffer(rom)
return buf
