def _gen_ring_pkt(opts, timestamp, src_id):
payload_nbits = opts.channel_bw
nports = opts.nterminals
id_type = mk_bits(clog2(nports))
pkt = mk_ring_pkt(nports, vc=2, payload_nbits=payload_nbits)()
pkt.payload = timestamp
dst_id = _gen_dst_id(opts.pattern, nports, src_id)
pkt.src = id_type(src_id)
pkt.dst = id_type(dst_id)
return pkt
def _mk_ring_net(opts):
nterminals = opts.nterminals
payload_nbits = opts.channel_bw
channel_lat = opts.channel_lat
Pos = mk_ring_pos(nterminals)
Pkt = mk_ring_pkt(nterminals, vc=2, payload_nbits=payload_nbits)
net = RingNetworkRTL(Pkt,
Pos,
nterminals,
channel_lat,
vc=2,
credit_line=2)
return net
def _test_simple(s, translation=''):
nterminals = 4
Pkt = mk_ring_pkt(nterminals)
src_pkts = mk_src_pkts(
nterminals,
[
# src dst opq vc payload
Pkt(3, 0, 0, 0, 0xfaceb00c),
])
dst_pkts = ringnet_fl(src_pkts)
th = TestHarness(Pkt, nterminals, src_pkts, dst_pkts)
cmdline_opts = {
'dump_vcd': False,
'test_verilog': translation,
'dump_vtb': False
}
run_sim(th, cmdline_opts)