def ConfigureXEM(self):
bitfile = BIT_FILE
assert os.path.exists(bitfile.encode('utf-8')), ".bit file NOT found!"
self.xem = ok.FrontPanel()
self.xem.OpenBySerial("")
assert self.xem.IsOpen(), "OpalKelly board NOT found!"
self.xem.LoadDefaultPLLConfiguration()
self.pll = ok.PLL22393()
self.pll.SetReference(48) #base clock frequency
self.baseRate = 200 #in MHz
self.pll.SetPLLParameters(0, self.baseRate, 48,
True) #multiply up to baseRate
self.pll.SetOutputSource(0, ok.PLL22393.ClkSrc_PLL0_0) #clk1
self.clkRate = 2 #mhz; 200 is fastest
self.pll.SetOutputDivider(0, int(self.baseRate / self.clkRate))
self.pll.SetOutputEnable(0, True)
## self.pll.SetOutputSource(1, ok.PLL22393.ClkSrc_PLL0_0) #clk2
## self.pll.SetOutputDivider(1, int(self.baseRate / self.clkRate)) #div4 = 100 mhz
## self.pll.SetOutputEnable(1, True)
self.xem.SetPLL22393Configuration(self.pll)
self.xem.ConfigureFPGA(bitfile.encode('utf-8'))
print(bitfile.encode('utf-8'))
def ConfigureXEM(self):
## dlg = wx.FileDialog( self, message="Open the Counters bitfile (counters.bit)",
## defaultDir="", defaultFile=BIT_FILE, wildcard="*.bit",
## style=wx.OPEN | wx.CHANGE_DIR )
# Show the dialog and retrieve the user response. If it is the OK response,
# process the data.
## if (dlg.ShowModal() == wx.ID_OK):
## bitfile = dlg.GetPath()
## defaultDir="../local/projects/fp_spindle_test/"
## defaultFile="fp_spindle_test.bit"
## defaultFile="counters_fp_muscle.bit"
bitfile = BIT_FILE
assert os.path.exists(bitfile.encode('utf-8')), ".bit file NOT found!"
self.xem = ok.FrontPanel()
self.xem.OpenBySerial("")
assert self.xem.IsOpen(), "OpalKelly board NOT found!"
self.xem.LoadDefaultPLLConfiguration()
self.pll = ok.PLL22393()
self.pll.SetReference(48) #base clock frequency
self.baseRate = 48 #in MHz
self.pll.SetPLLParameters(0, self.baseRate, 48,
True) #multiply up to baseRate
self.pll.SetOutputSource(0, ok.PLL22393.ClkSrc_PLL0_0) #clk1
self.clkRate = 40 #mhz; 200 is fastest
self.pll.SetOutputDivider(0, int(self.baseRate / self.clkRate))
self.pll.SetOutputEnable(0, True)
## self.pll.SetOutputSource(1, ok.PLL22393.ClkSrc_PLL0_0) #clk2
## self.pll.SetOutputDivider(1, int(self.baseRate / self.clkRate)) #div4 = 100 mhz
## self.pll.SetOutputEnable(1, True)
self.xem.SetPLL22393Configuration(self.pll)
## self.xem.SetEepromPLL22393Configuration(self.pll)
self.xem.ConfigureFPGA(bitfile.encode('utf-8'))
print(bitfile.encode('utf-8'))