def test_allocation_get_channel():
program = Program([Push(0), Pop(0), Push(1), Push(2), Pop(2)])
assert program.get_channel_for_port_key(0, KEY_CKS_DATA) == 0
assert program.get_channel_for_port_key(0, KEY_CKS_CONTROL) == 3
assert program.get_channel_for_port_key(1, KEY_CKR_DATA) is None
assert program.get_channel_for_port_key(2, KEY_CKS_DATA) == 2
def test_codegen_device(file_tester):
program = Program([
Push(0, "short", 8),
Pop(0),
Push(1),
Pop(2, "char", 8),
Broadcast(3, "float", 64),
Broadcast(4, "int"),
Push(5, "double", 32),
Reduce(6, "float", 16, "add"),
Scatter(7, "double"),
Gather(8, "char")
])
mapping = ProgramMapping([program], {
"n1:f1": program,
"n1:f2": program,
"n2:f1": program,
"n3:f1": program
})
connections = {
("n1:f1", 0): ("n1:f2", 0),
("n1:f2", 1): ("n2:f1", 1),
("n1:f2", 2): ("n3:f1", 1),
("n2:f1", 0): ("n1:f1", 1),
}
ctx = create_routing_context(connections, mapping)
file_tester.check(
"smi-device-1.h",
generate_program_device(ctx.fpgas[0], ctx.fpgas, ctx.graph, 4))
def test_cks_table_double_rail2():
program = Program([Push(0), Pop(0), Push(1), Pop(1)])
ctx = get_routing_ctx(
program, {
("N:F0", 1): ("N:F1", 0),
("N:F0", 3): ("N:F1", 2),
("N:F1", 1): ("N:F2", 0),
("N:F1", 3): ("N:F2", 2),
("N:F2", 1): ("N:F3", 0),
("N:F2", 3): ("N:F3", 2),
("N:F3", 1): ("N:F4", 0),
("N:F3", 3): ("N:F4", 2),
("N:F4", 1): ("N:F5", 0),
("N:F4", 3): ("N:F5", 2),
("N:F5", 1): ("N:F0", 0),
("N:F5", 3): ("N:F0", 2),
})
graph, routes, fpgas = (ctx.graph, ctx.routes, ctx.fpgas)
fpga = get_fpga(fpgas, "N:F4")
tables = cks_routing_tables(fpga, fpgas, routes)
check_fpga_tables(fpga, tables,
[[['0->1', '0->1'], ['QSFP', 'QSFP'], ['QSFP', 'QSFP'],
['0->2', 'QSFP'], ['CKR', 'CKR'], ['0->3', '0->1']],
[['QSFP', 'QSFP'], ['QSFP', '1->0'], ['1->0', '1->0'],
['1->0', '1->2'], ['CKR', 'CKR'], ['QSFP', 'QSFP']],
[['2->1', '2->1'], ['QSFP', 'QSFP'], ['QSFP', 'QSFP'],
['QSFP', 'QSFP'], ['CKR', 'CKR'], ['2->3', '2->1']],
[['QSFP', 'QSFP'], ['QSFP', 'QSFP'], ['3->0', '3->0'],
['3->0', '3->0'], ['CKR', 'CKR'], ['QSFP', 'QSFP']]])
def test_cks_table_double_rail():
program = Program([Push(0), Pop(0), Push(1), Pop(1)])
ctx = get_routing_ctx(
program, {
("N1:F0", 1): ("N1:F1", 0),
("N1:F0", 3): ("N1:F1", 2),
("N1:F1", 1): ("N2:F0", 0),
("N1:F1", 3): ("N2:F0", 2),
("N2:F0", 1): ("N2:F1", 0),
("N2:F0", 3): ("N2:F1", 2),
("N2:F1", 1): ("N1:F0", 0),
("N2:F1", 3): ("N1:F0", 2),
})
graph, routes, fpgas = (ctx.graph, ctx.routes, ctx.fpgas)
fpga = get_fpga(fpgas, "N1:F0")
tables = cks_routing_tables(fpga, fpgas, routes)
check_fpga_tables(fpga, tables, [
[["CKR", "CKR"], ["0->1", "0->1"], ["QSFP", "QSFP"], ["0->2", "QSFP"]],
[["CKR", "CKR"], ["QSFP", "1->3"], ["QSFP", "1->0"], ["1->0", "1->0"]],
[["CKR", "CKR"], ["2->1", "2->1"], ["QSFP", "QSFP"], ["QSFP", "QSFP"]],
[["CKR", "CKR"], ["QSFP", "QSFP"], ["QSFP", "QSFP"], ["3->0", "3->0"]]
])
fpga = get_fpga(fpgas, "N1:F1")
tables = cks_routing_tables(fpga, fpgas, routes)
check_fpga_tables(fpga, tables, [
[["QSFP", "QSFP"], ["CKR", "CKR"], ["0->1", "0->1"], ["QSFP", "QSFP"]],
[["1->0", "1->2"], ["CKR", "CKR"], ["QSFP", "1->3"], ["QSFP", "QSFP"]],
[["QSFP", "QSFP"], ["CKR", "CKR"], ["2->1", "2->1"], ["QSFP", "QSFP"]],
[["3->0", "3->0"], ["CKR", "CKR"], ["QSFP", "QSFP"], ["QSFP", "QSFP"]]
])
def test_ckr_table():
program = Program([Push(0), Pop(1), Push(2), Pop(3), Pop(4)])
fpga = FPGA("n", "f", program)
def get_table(index):
return ckr_routing_table(fpga.channels[index], CHANNELS_PER_FPGA,
program).get_data()
assert get_table(0) == [0, 3, 4, 0, 0, 5, 1, 0, 2, 0]
assert get_table(1) == [0, 3, 1, 0, 0, 1, 4, 0, 2, 0]
assert get_table(2) == [0, 3, 1, 0, 0, 1, 2, 0, 4, 0]
assert get_table(3) == [0, 4, 1, 0, 0, 1, 2, 0, 3, 0]
def test_ckr_table():
program = Program([Push(0), Pop(1), Push(2), Pop(3), Pop(4)])
fpga = FPGA("n", "f", program)
assert ckr_routing_table(fpga.channels[0], CHANNELS_PER_FPGA,
program) == [0, 3, 4, 0, 0, 5, 1, 0, 2, 0]
assert ckr_routing_table(fpga.channels[1], CHANNELS_PER_FPGA,
program) == [0, 3, 1, 0, 0, 1, 4, 0, 2, 0]
assert ckr_routing_table(fpga.channels[2], CHANNELS_PER_FPGA,
program) == [0, 3, 1, 0, 0, 1, 2, 0, 4, 0]
assert ckr_routing_table(fpga.channels[3], CHANNELS_PER_FPGA,
program) == [0, 4, 1, 0, 0, 1, 2, 0, 3, 0]
def test_codegen_host(file_tester):
program = Program([
Push(0),
Pop(0),
Push(1),
Pop(2),
Broadcast(3),
Broadcast(4),
Push(5),
Reduce(6, "float", 16, "min")
])
file_tester.check("smi-host-1.h",
generate_program_host([("program", program)]))
def test_cks_table_2():
program = Program([Push(0), Push(1)])
ctx = get_routing_ctx(program, {
("N0:FA", 0): ("N0:FB", 0),
("N0:FA", 3): ("N0:FB", 3)
})
graph, routes, fpgas = (ctx.graph, ctx.routes, ctx.fpgas)
fa = get_fpga(fpgas, "N0:FA")
tables = cks_routing_tables(fa, fpgas, routes)
check_fpga_tables(fa, tables, [[["CKR", "CKR"], ["QSFP", "QSFP"]],
[["CKR", "CKR"], ["1->0", "1->3"]],
[["CKR", "CKR"], ["2->0", "2->0"]],
[["CKR", "CKR"], ["QSFP", "QSFP"]]])
def test_cks_table():
ctx = get_routing_ctx(Program([Push(0), Push(1), Pop(2)]), {
("N0:F0", 0): ("N0:F1", 0),
("N1:F0", 0): ("N0:F0", 1)
})
graph, routes, fpgas = (ctx.graph, ctx.routes, ctx.fpgas)
a = get_channel(graph, "N0:F0", 0)
assert cks_routing_table(routes, fpgas, a) == [1, 0, 2]
b = get_channel(graph, "N0:F0", 1)
assert cks_routing_table(routes, fpgas, b) == [1, 2, 0]
c = get_channel(graph, "N0:F1", 0)
assert cks_routing_table(routes, fpgas, c) == [0, 1, 0]
d = get_channel(graph, "N1:F0", 0)
assert cks_routing_table(routes, fpgas, d) == [0, 0, 1]
def test_allocation_channel_to_ports():
program = Program([Push(0), Pop(0), Push(1), Push(2), Pop(2)])
ops = program.operations
assert program.get_channel_allocations(0) == [
(ops[0], "cks_data"),
(ops[4], "cks_control"),
(ops[1], "ckr_data"),
(ops[3], "ckr_control"),
]
assert program.get_channel_allocations(1) == [
(ops[2], "cks_data"),
(ops[4], "ckr_data"),
]
assert program.get_channel_allocations(2) == [
(ops[3], "cks_data"),
(ops[0], "ckr_control"),
]
assert program.get_channel_allocations(3) == [
(ops[1], "cks_control"),
(ops[2], "ckr_control"),
]
def test_allocation_fail():
with pytest.raises(FailedAllocation):
Program([Push(0), Broadcast(0)])