def writeRegister(self, name, value, fpga=0):
cmds = padeCommon.regCmd(self.registers[str(name)], value, fpga)
for cmd in cmds:
self.client.sendLine(cmd)
chkfn = lambda : self.chkRegister(name, value)
self.readRegister(name, chkfn,fpga)
def connectReadAllSec(host, port, regs):
s = socket.create_connection((host, port))
fd = s.fileno()
ep = select.epoll()
ep.register(fd, select.EPOLLIN )
resps = {}
msgid = 0
for name, reg in regs.iteritems():
cmd = padeCommon.regCmd(reg)
resps[name] = []
for c in cmd:
written = s.send(c+'\r\n')
events = ep.poll(1)
for fileno, ev in events:
if ev & select.EPOLLIN:
buf = s.recv(128)
resps[name].append(buf.strip())
if len(events) == 0:
print 'Failed to read: {0}'.format(name)
for name,resp in resps.iteritems():
print '{0}: {1}'.format(name, resp)
s.close()
def readRegister(self, name, cb, fpga=0):
# I don't like this idiom, I'll have to see if I can come up with
# a clearer way of expressing it
self.client.handle_msg = self.handle_register
cmds = padeCommon.regCmd(self.registers[str(name)], None, fpga)
self.readcb = cb
self.cbs = deque()
upper = False
for cmd in cmds:
# We'll only have two cmds, in an n>2 case this won't work correctly
d = defer.Deferred()
d.addCallback(functools.partial(self.readRegisterBase, str(name), upper))
self.cbs.append(d)
upper = True
for cmd in cmds:
self.client.sendLine(cmd)
def test_complex_reg_read(self):
cmds = padeCommon.regCmd(self.registers['SDRAM_WritePointer'])
self.assertEqual(cmds, ['rd 2', 'rd 3'])
def test_simple_reg_read(self):
cmds = padeCommon.regCmd(self.registers['SDRAM_read'])
self.assertEqual(cmds, ['rd 7'])