def build(self):
board = pcbnew.BOARD()
# outline
PcbPolygon(self.outline).build(board)
# Add holes
for h in self.holes:
h.build(board)
# Add ground plane
signals = {}
if self.fill_name:
fill_net = pcbnew.NETINFO_ITEM(board, self.fill_name)
board.Add(fill_net)
signals[self.fill_name] = fill_net
item = pcbnew.ZONE(board, False)
poly = pcbnew.wxPoint_Vector()
for x, y in self.outline.exterior.coords:
poly.append(pcbnew.wxPointMM(x, y))
item.AddPolygon(poly)
item.SetNet(fill_net)
lset = pcbnew.LSET()
lset.AddLayer(pcbnew.F_Cu)
lset.AddLayer(pcbnew.B_Cu)
item.SetLayerSet(lset)
board.Add(item)
for component in self.components:
component.build(board, signals)
return board
def __init__(self):
"""
Initializes empty panel.
"""
self.board = pcbnew.BOARD()
self.boardCounter = 0
self.boardSubstrate = Substrate([]) # Keep substrate in internal representation,
# Draw it just before saving
self.hVCuts = set() # Keep V-cuts as numbers and append them just before saving
self.vVCuts = set() # to make them truly span the whole panel
def polygon_to_kicad_file():
"""Build a kicad file containing an empty PCB with the provided shape."""
board = pcbnew.BOARD()
board.Add(kicad_circle(0, 0, 100))
board.Add(kicad_circle(0, 0, 50))
tf = tempfile.NamedTemporaryFile()
board.Save(tf.name)
return tf
def __init__(self):
"""
Initializes empty panel.
"""
self.board = pcbnew.BOARD()
self.substrates = [
] # Substrates of the individual boards; e.g. for masking
self.boardCounter = 0
self.boardSubstrate = Substrate(
[]) # Keep substrate in internal representation,
# Draw it just before saving
self.hVCuts = set(
) # Keep V-cuts as numbers and append them just before saving
self.vVCuts = set() # to make them truly span the whole panel
self.copperLayerCount = None
self.zonesToRefill = pcbnew.ZONE_CONTAINERS()
def main():
with open(output_directory + project_name + "_v2.pro", mode="w") as project_file:
project_file.write(project_template)
with open(layout_file_name) as lautout_file:
layout = json.load(lautout_file)
switch_sch = codecs.open(output_directory + project_name + "_v2.sch", mode="w", encoding='utf-8')
switch_sch.write(schem_template_header)
pcb = pcbnew.BOARD()
x, y = x_origin, y_origin
i = 1
timestamp = time()
for row in layout:
if not isinstance(row, list):
continue
x = x_origin
y_offset = 0.0
width = 1.0
for col in row:
if isinstance(col, dict):
y_offset = (float(col.get("h", 1)) - 1) / 2
width = float(col.get("w", 1))
x += float(col.get("x", 0))
y += float(col.get("y", 0))
print col, x, y, width, y_offset
elif isinstance(col, six.string_types):
print col, x, y, width, y_offset
ref = "SW_X%dY%d" % (x, y)
if col.split() and col.split()[0].isalnum():
ref = u"SW_" + col.split()[0]
ref += "_%d" % i
x_offset = (width - 1.0) / 2
place_footprint(pcb, x + x_offset, y + y_offset, ref, i)
add_to_schematic(switch_sch, x + x_offset, y + y_offset, timestamp + i, ref)
x += width
width = 1.0
i += 1
y += 1
pcb.Save(output_directory + project_name + "_v2.kicad_pcb")
switch_sch.write(schem_template_footer)
switch_sch.close()
def test_eq(self):
bp = _pcbnew.BOARD()
b1 = Board(bp)
b2 = Board(bp.GetBoard())
self.assertEqual(b1, b2)
def test_init_param(self):
b_native = _pcbnew.BOARD()
b = Board(b_native)
self.assertIs(b_native, b.get_native())
self.assertEqual(_pcbnew.BOARD, type(b.get_native()))
def __init__(self, board=None):
"""Convenience wrapper for pcbnew Board"""
if board == None:
# if no board is given create a new board
board = pcbnew.BOARD()
self._board = board
def kinet2pcb(netlist_origin, brd_filename):
"""Create a .kicad_pcb from a KiCad netlist file."""
# Get the global and local fp-lib-table file URIs.
fp_libs = LibURIs(get_global_fp_lib_table_fn(),
os.path.join(".", "fp-lib-table"))
# Create a blank KiCad PCB.
brd = pcbnew.BOARD()
# Get the netlist.
if isinstance(netlist_origin, type('')):
# Parse the netlist into an object if given a file name string.
netlist = kinparse.parse_netlist(netlist_origin)
else:
# otherwise, the netlist is already an object that can be processed directly.
netlist = netlist_origin
# Add the components in the netlist to the PCB.
for part in netlist.parts:
# Get the library and footprint name for the part.
fp_lib, fp_name = part.footprint.split(":")
# Get the URI of the library directory.
lib_uri = fp_libs[fp_lib]
# Create a module from the footprint file.
fp = pcbnew.FootprintLoad(lib_uri, fp_name)
# Set the module parameters based on the part data.
#import pdb; pdb.set_trace()
fp.SetParent(brd)
fp.SetReference(part.ref)
fp.SetValue(part.value)
# fp.SetTimeStamp(part.sheetpath.tstamps)
try:
fp.SetPath(part.sheetpath.names)
except AttributeError:
pass
# Add the module to the PCB.
brd.Add(fp)
# Add the nets in the netlist to the PCB.
cnct = brd.GetConnectivity()
for net in netlist.nets:
# Create a net with the current net name.
pcb_net = pcbnew.NETINFO_ITEM(brd, net.name)
# Add the net to the PCB.
brd.Add(pcb_net)
# Connect the part pins on the netlist net to the PCB net.
for pin in net.pins:
# Find the PCB module pad for the current part pin.
module = brd.FindModuleByReference(pin.ref)
pad = module.FindPadByName(pin.num)
# Connect the pad to the PCB net.
cnct.Add(pad)
pad.SetNet(pcb_net)
# Recalculate the PCB part and net data.
brd.BuildListOfNets()
cnct.RecalculateRatsnest()
pcbnew.Refresh()
# Place the board parts into non-overlapping areas that follow the design hierarchy.
hierplace.hier_place(brd)
# Save the PCB into the KiCad PCB file.
pcbnew.SaveBoard(brd_filename, brd)
def add_outline_to_board(pcb_filename,
left_mm,
top_mm,
width_mm,
height_mm,
usb_cutout_position=-1,
usb_cutout_width=-1,
modify_existing=True,
margin_mm=0,
corner_radius_mm=3):
l = left_mm * MM_TO_KC
t = top_mm * MM_TO_KC
r = (left_mm + width_mm) * MM_TO_KC
b = (top_mm + height_mm) * MM_TO_KC
l = int(l)
t = int(t)
r = int(r)
b = int(b)
margin_kc = margin_mm * MM_TO_KC
corner_rad_kc = corner_radius_mm * MM_TO_KC
points = [
(l - margin_kc, t - margin_kc),
(r + margin_kc, t - margin_kc),
(r + margin_kc, b + margin_kc),
(l - margin_kc, b + margin_kc),
]
if modify_existing:
pcb = pcbnew.LoadBoard(pcb_filename)
else:
pcb = pcbnew.BOARD()
if usb_cutout_position >= 0:
usb_cutout_left = (usb_cutout_position -
usb_cutout_width / 2) * MM_TO_KC
usb_cutout_right = (usb_cutout_position +
usb_cutout_width / 2) * MM_TO_KC
draw_segment(pcb, points[0][0] + corner_rad_kc, points[0][1],
usb_cutout_left, points[0][1])
draw_segment(pcb, usb_cutout_right, points[1][1],
points[1][0] - corner_rad_kc, points[1][1])
else:
draw_segment(pcb, points[0][0] + corner_rad_kc, points[0][1],
points[1][0] - corner_rad_kc, points[1][1])
draw_segment(pcb, points[1][0], points[1][1] + corner_rad_kc, points[2][0],
points[2][1] - corner_rad_kc)
draw_segment(pcb, points[2][0] - corner_rad_kc, points[2][1],
points[3][0] + corner_rad_kc, points[3][1])
draw_segment(pcb, points[3][0], points[3][1] - corner_rad_kc, points[0][0],
points[0][1] + corner_rad_kc)
draw_arc(pcb, points[0][0] + corner_rad_kc, points[0][1] + corner_rad_kc,
points[0][0], points[0][1] + corner_rad_kc, 90)
draw_arc(pcb, points[1][0] - corner_rad_kc, points[1][1] + corner_rad_kc,
points[1][0] - corner_rad_kc, points[1][1], 90)
draw_arc(pcb, points[2][0] - corner_rad_kc, points[2][1] - corner_rad_kc,
points[2][0], points[2][1] - corner_rad_kc, 90)
draw_arc(pcb, points[3][0] + corner_rad_kc, points[3][1] - corner_rad_kc,
points[3][0] + corner_rad_kc, points[3][1], 90)
pcbnew.SaveBoard(pcb_filename, pcb)