def loadNewInstance(self,libraryname,componentname,
componentversion,instancename):
""" Load a new component from library
"""
project = self.getParent()
# verify component name
if project.getName() == instancename:
raise Error("Instance name can't be the same name as projectname",0)
# test if component exist
if not sy.fileExist(
project.library.getLibraryPath(libraryname)+\
"/"+componentname):
raise Error("No component with name "+\
libraryname+"."+componentname,0)
#test if several componentversion
if componentversion==None:
if len(project.getComponentVersionList(
libraryname,componentname))>1:
raise Error("Component version must be chosen :"+\
str(project.getComponentVersionList(
libraryname,componentname)),0)
else:
try:
componentversion = project.getComponentVersionList(
libraryname,componentname)[0]
except IndexError:
raise Error("No xml description of component",0)
if instancename == None:
instancename = componentname+\
"%02d"%project.getInstanceAvailability(
componentname)
#copy and rename directory
sy.copyDirectory(project.library.getLibraryPath( libraryname)+\
"/"+componentname,settings.projectpath + COMPONENTSPATH)
try:
sy.renameDirectory(settings.projectpath+COMPONENTSPATH+\
"/"+componentname,\
settings.projectpath + COMPONENTSPATH+"/" + instancename)
except Error: # if directory exist
pass
#Rename xml file
sy.renameFile(settings.projectpath+COMPONENTSPATH+"/"\
+instancename+"/"+componentversion+XMLEXT,\
settings.projectpath+COMPONENTSPATH+"/"+instancename+"/"\
+instancename + XMLEXT)
#load component
self.loadInstance(instancename)
#Connect platform connection
self.autoconnectPin()
def generateTemplate():
""" generate Template Testbench
"""
filename = settings.projectpath+SIMULATIONPATH+"/top_"+ settings.active_project.getName()+"_tb"+VHDLEXT
clockportlist = settings.active_project.getListClockPorts()
if len(clockportlist) == 0:
raise Error("No external clock signal found",0)
if len(clockportlist) != 1:
display.msg("More than one external clock in design",1)
clockport = clockportlist[0]
clockname = clockport.getParent().getParent().getInstanceName()+"_"+clockport.getName()
###################
# header
out = header()
out = out + include()
out = out + entity()
out = out + architecturehead()
freq = clockport.getDestinationPort().getFreq()
clockhalfperiode= (1000/float(freq))/2
out = out + constant(clockhalfperiode)
portlist = settings.active_project.getPlatform().getConnectPortsList()
out = out + signals(portlist)
out = out + declareTop(portlist)
out = out + beginarch()
out = out + connectTop(portlist)
out = out + stimulis()
out = out + "\n"
out = out + clock(clockname)
out = out + "\n"
out = out + endarch()
#######################
# save file
if sy.fileExist(filename):
display.msg("[WARNING] File exist, file renamed in "+filename+"old",0)
sy.renameFile(filename,filename+"old")
try:
file = open(filename,"w")
except IOError, e:
raise e
