class adder:
def __init__(self):
self.i_a3 = Port(uint3, 'in', protocol='valid')
self.i_b3 = Port(uint3, 'in', protocol='valid')
self.o_r4 = Port(uint4, 'out', protocol='valid')
self.append_worker(self.adder_worker)
def adder_worker(self):
while polyphony.is_worker_running():
a3: uint4 = self.i_a3.rd()
b3: uint4 = self.i_b3.rd()
r4: uint4 = a3 + b3
self.o_r4(r4)
class Sub:
def __init__(self):
self.p = Port(int, 'in')
self.append_worker(self.w)
def w(self):
x = self.p.rd()
class UartBridge:
def __init__(self):
self.rx_data = Port(bit8, 'in')
self.rx_ready = Port(bit, 'in')
self.rx_idle = Port(bit, 'in')
self.tx_start = Port(bit, 'out', 0)
self.tx_data = Port(bit8, 'out', 0)
self.tx_busy = Port(bit, 'in')
def tx_char(self, char_c):
wait_value(0, self.tx_busy)
self.tx_data.wr(char_c)
self.tx_start.wr(1)
clkfence()
wait_value(1, self.tx_busy)
self.tx_start.wr(0)
def flush_tx(self):
wait_value(0, self.tx_busy)
def rx_char(self):
wait_value(1, self.rx_ready)
data: bit8 = self.rx_data.rd()
return data
class object_if01:
def __init__(self):
self.mode = Port(int, 'in', protocol='ready_valid')
self.result = Port(int, 'out', protocol='ready_valid')
self.a = Object()
self.b = Object()
self.c = Object()
self.append_worker(self.main)
def read(self, obj0, obj1):
x = obj0.read()
y = obj1.read()
return x - y
def main(self):
while is_worker_running():
mode = self.mode.rd()
ret = 0
if mode == 0:
ret = self.read(self.a, self.b)
elif mode == 1:
ret = self.read(self.b, self.c)
elif mode == 2:
pass
else:
ret = self.read(self.c, self.a)
self.result.wr(ret)
class io03:
def __init__(self, x):
d = [x] * 10
self.p = Port(bool, 'any', init=d[0])
self.append_worker(self.w)
def w(self):
d = self.p.rd()
class spi_master:
def __init__(self):
self.sclk = Port(bit, 'out')
self.mosi = Port(bit, 'out')
self.miso = Port(bit, 'in')
self.cs_n = Port(bit, 'out', init=1)
self.data8 = Port(uint8, 'out', protocol='ready_valid')
self.append_worker(self.worker)
def write_data(self, data):
self.cs_n.wr(0)
clkfence()
for i in range(8):
clkfence()
self.sclk.wr(0)
bit1 = (data >> (7 - i)) & 1
self.mosi.wr(bit1)
clksleep(1)
self.sclk.wr(1)
self.sclk.wr(0)
clkfence()
def read_data(self):
#self.cs_n.wr(0)
#clksleep(1)
data: uint8 = 0
#self.sclk.wr(0)
for i in range(8):
data <<= 1
clkfence()
self.sclk.wr(1)
clkfence()
bit1 = self.miso.rd() & 1
clkfence()
self.sclk.wr(0)
data |= bit1
clksleep(1)
self.cs_n.wr(1)
return data
def worker(self):
#while polyphony.is_worker_running():
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
self.write_data(0x34)
data: uint8 = self.read_data()
clksleep(1)
self.data8.wr(data)
class Protocol02:
def __init__(self):
self.i = Port(int8, 'in', init=0, protocol='ready_valid')
self.o = Port(int8, 'out', init=0, protocol='ready_valid')
self.append_worker(self.main)
def main(self):
t = self.i.rd()
self.o.wr(t * t)
class io_read_conflict03:
def __init__(self):
self.p = Port(int, 'in', protocol='valid')
self.append_worker(self.w)
self.append_worker(self.w)
def w(self):
data = self.p.rd()
print(data)
class Protocol04:
def __init__(self):
self.i1 = Port(int8, 'in', init=0, protocol='valid')
self.i2 = Port(int8, 'in', init=0, protocol='valid')
self.i3 = Port(int8, 'in', init=0, protocol='valid')
self.o1 = Port(int8, 'out', init=0, protocol='valid')
self.o2 = Port(int8, 'out', init=0, protocol='valid')
self.o3 = Port(int8, 'out', init=0, protocol='valid')
self.append_worker(self.main)
def main(self):
while is_worker_running():
with rule(scheduling='parallel'):
t1 = self.i1.rd()
t2 = self.i2.rd()
t3 = self.i3.rd()
self.o1.wr(t1 * t1)
self.o2.wr(t2 * t2)
self.o3.wr(t3 * t3)
class Submodule:
def __init__(self, param):
self.i = Port(int8, 'in')
self.o = Port(int8, 'out')
self.param = param
self.append_worker(self.sub_worker)
def sub_worker(self):
while is_worker_running():
v = self.i.rd() * self.param
self.o.wr(v)
class Protocol01:
def __init__(self):
self.i = Port(int8, 'in', init=0, protocol='valid')
self.o = Port(int8, 'out', init=0, protocol='ready_valid')
self.append_worker(self.main)
def main(self):
# Reading from the "valid" protocol port is blocked until the port becomes 'valid'.
t = self.i.rd()
# Writing to the 'ready_valid' protocol port makes the port 'valid'.
# And if the port is not 'ready', it is blocked until the port becomes 'ready'.
self.o.wr(t * t)
class uart_cmd_server:
def __init__(self):
self.status_port = Port(bit32, 'out', init=STATUS_BUSY_FLAG)
self.cmd_in = Port(bit32, 'in')
self.cmd_reply = Port(bit32, 'out', init=0)
self.uart_data_in = Port(bit32, 'in')
self.uart_data_out = Port(bit32, 'out')
self.uart_bridge = UartBridge()
self.append_worker(self.worker)
def worker(self):
self.status_port.wr(0)
data: bit32 = 0
while is_worker_running():
while True:
cmd: bit32 = self.cmd_in.rd()
if cmd != IO_CMD_NOP:
self.status_port.wr(STATUS_BUSY_FLAG)
break
if cmd == IO_CMD_TX_UART:
data = self.uart_data_in.rd()
self.uart_bridge.tx_char(data & 0xFF)
elif cmd == IO_CMD_RX_UART:
data = self.uart_bridge.rx_char()
self.uart_data_out.wr(data & 0xFF)
elif cmd == IO_CMD_TX_FLUSH_UART:
self.uart_bridge.flush_tx()
data = IO_CMD_REPLY_FLAG | cmd
self.cmd_reply.wr(data)
self.status_port.wr(0)
while True:
cmd = self.cmd_in.rd()
if cmd == IO_CMD_NOP:
break
data = IO_CMD_REPLY_FLAG | IO_CMD_NOP
self.cmd_reply.wr(data)
class AD7091R_SPIC:
def __init__(self):
self.sclk = Port(bit, 'out')
self.sdo = Port(bit, 'in')
self.sdi = Port(bit, 'out')
self.convst_n = Port(bit, 'out', init=1)
self.cs_n = Port(bit, 'out', init=1)
self.dout = Port(uint12, 'out')
self.chout = Port(uint3, 'out')
self.din = Port(uint16, 'in')
self.data_ready = Port(bit, 'out')
self.append_worker(self.main)
def main(self):
while polyphony.is_worker_running():
self.convst_n.wr(1)
self.cs_n.wr(1)
self.data_ready.wr(0)
clkfence()
self.convst_n.wr(0)
clksleep(CONVST_PULSE_CYCLE)
self.convst_n.wr(1)
clksleep(CONVERSION_CYCLE)
# starting ADC I/O
self.cs_n.wr(0)
sdo_tmp = 0
clksleep(1)
for i in range(16):
self.sclk.wr(0)
clkfence()
sdi_tmp = 1 if (self.din() & (1 << (15 - i))) else 0
self.sdi.wr(sdi_tmp)
clksleep(1)
self.sclk.wr(1)
clkfence()
sdo_d = self.sdo.rd()
sdo_tmp = sdo_tmp << 1 | sdo_d
#print('sdo read!', i, sdo_d)
self.sclk.wr(0)
self.dout.wr(sdo_tmp & 0x0fff)
self.chout.wr((sdo_tmp & 0x7000) >> 12)
self.cs_n.wr(1)
clkfence()
self.data_ready.wr(1)
class pmod_als:
def __init__(self):
self.sclk = Port(bit, 'out')
self.miso = Port(bit, 'in')
self.cs_n = Port(bit, 'out', init=1)
self.data16 = Port(uint16, 'out', protocol='ready_valid')
self.append_worker(self.worker)
def read_data(self):
self.cs_n.wr(0)
clksleep(1)
data: uint16 = 0
self.sclk.wr(0)
for i in range(16):
data <<= 1
clksleep(1)
self.sclk.wr(1)
clksleep(1)
bit1 = self.miso.rd() & 1
clkfence()
self.sclk.wr(0)
data |= bit1
clksleep(1)
self.cs_n.wr(1)
return data
def worker(self):
while polyphony.is_worker_running():
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
data: uint16 = self.read_data()
clksleep(1)
self.data16.wr(data)
class dac_ds:
def __init__(self, use_sin_table=False):
self.i_port = Port(int8, 'in', protocol='valid')
self.o_port = Port(int8, 'out', protocol='ready_valid')
self.append_worker(self.dac_ds_worker, use_sin_table, self.i_port,
self.o_port)
print("__init__")
def dac_ds_worker(self, use_sin_table, i_port, o_port):
i = 0
ti = 0
while polyphony.is_worker_running():
if use_sin_table:
v = table[ti]
if ti == (SIN_CYCLE - 1):
ti = 0
else:
ti = ti + 1
else:
#wait_value(1, self.i_detect)
v = self.i_port.rd()
self.o_port(v)
class queue06:
def __init__(self):
self.in_cmd = Queue(int8, 'in', maxsize=2)
self.din0 = Port(int, 'in')
self.din1 = Port(int, 'in')
self.out_q = Queue(int8, 'out', maxsize=2)
self.append_worker(self.main)
def calc(self, cmd):
if cmd == 0:
return self.din0.rd() + self.din1.rd()
elif cmd == 1:
return self.din0.rd() - self.din1.rd()
elif cmd == 2:
return self.din0.rd() * self.din1.rd()
return 0
def main(self):
while is_worker_running():
if not self.in_cmd.empty():
cmd = self.in_cmd.rd()
ret = self.calc(cmd)
if not self.out_q.full():
self.out_q.wr(ret)
class system_bus:
def __init__(self):
self.stb = Port(bit, 'out', init=0)
self.rw = Port(bit, 'out')
self.addr = Port(uint8, 'out')
self.data_out = Port(uint8, 'out')
self.data_in = Port(uint8, 'in')
self.ack = Port(bit, 'in')
self.sbus_reset = Port(bit, 'out', init=0)
self.sbus_ipload = Port(bit, 'out', init=0)
self.sbus_ipdone = Port(bit, 'in')
self.led = Port(bit, 'out')
self.debug = Port(uint3, 'out')
self.append_worker(self.worker)
def write_data(self, addr: uint8, data: uint8):
self.rw(1)
self.addr(addr)
self.data_out(data)
clkfence()
self.stb(1)
clkfence()
wait_value(1, self.ack)
clkfence()
self.stb(0)
def read_data(self, addr: uint8):
data: uint8 = 0
self.rw(0)
self.addr(addr)
clkfence()
self.stb(1)
clkfence()
wait_value(1, self.ack)
data = self.data_in.rd()
clkfence()
self.stb(0)
return data
def read_spi_data16(self):
debug_v: uint3 = 0
debug_v = 4
#self.debug.wr(4)
self.write_data(0x06, 0x18)
self.write_data(0x0A, 0xC0)
self.write_data(0x0D, 0xFF)
while True:
irq_status = self.read_data(0x06)
irq_trdy = (irq_status >> 4) & 1
if irq_trdy == 1:
self.write_data(0x06, 0x10)
break
self.write_data(0x0D, 0xFF)
#self.debug.wr(5)
debug_v = 1
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
debug_v = 7 ^ debug_v
# self.debug.wr(debug_v)
if irq_rrdy == 1:
self.write_data(0x06, 0x08)
break
data0 = self.read_data(0x0E) << 8
debug_v = 2
#self.debug.wr(2)
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
if irq_rrdy == 1:
debug_v = 4 ^ debug_v
#self.debug.wr(debug_v)
self.write_data(0x06, 0x08)
break
data1 = self.read_data(0x0E)
#self.debug.wr(1)
self.write_data(0x0A, 0x80)
return (data0 | data1)
def worker(self):
self.sbus_reset.wr(1)
clksleep(8)
self.sbus_reset.wr(0)
self.sbus_ipload(1)
self.debug.wr(4)
self._wait()
wait_value(1, self.sbus_ipdone)
self.sbus_ipload(0)
self.debug.wr(0)
clksleep(8)
self.write_data(0x07, 0x18)
self.write_data(0x0F, 2)
self.write_data(0x09, 0x80)
self.write_data(0x0A, 0xC0)
self.write_data(0x0B, 0x02)
self.write_data(0x0A, 0xC0)
self.write_data(0x0D, 0x35)
self.debug.wr(4)
irq_status = 0
while True:
irq_status = self.read_data(0x06)
irq_trdy = (irq_status >> 4) & 1
if irq_trdy == 1:
self.write_data(0x06, 0x10)
break
#self.debug.wr((irq_status >> 3) & 3)
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
if irq_rrdy == 1:
self.write_data(0x06, irq_status)
break
# self.write_data(0x0D, 0x5A)
# self.debug.wr((irq_status >> 3) & 3)
# #self.debug.wr(1)
#
# while True:
# irq_status = self.read_data(0x06)
# irq_trdy = (irq_status >> 4) & 1
# if irq_trdy == 1 :
# self.write_data(0x06, 0x10)
# #break
# irq_rrdy = (irq_status >> 3) & 1
# if irq_rrdy == 1 :
# self.write_data(0x06, 0x08)
# break
#
# self.debug.wr(1)
#self._wait()
#while True:
# irq_status = self.read_data(0x06)
# if irq_status == 0 :
# break
# self._wait()
# self.write_data(0x06, irq_status)
# self._wait()
#self.debug.wr((irq_status >> 3) & 2)
#self._wait()
self.write_data(0x0A, 0x80)
#----------------------------------------------------
self.write_data(0x0A, 0xC0)
self.write_data(0x0D, 0x12)
self.debug.wr(7)
irq_status = 0
while True:
irq_status = self.read_data(0x06)
irq_trdy = (irq_status >> 4) & 1
if irq_trdy == 1:
self.write_data(0x0D, 0xAA)
self.write_data(0x06, 0x10)
break
#self.debug.wr((irq_status >> 3) & 2)
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
if irq_rrdy == 1:
self.write_data(0x06, 0x08)
break
#self.debug.wr((irq_status >> 3) & 2)
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
if irq_rrdy == 1:
self.write_data(0x06, 0x08)
break
self.write_data(0x0A, 0x80)
clkfence()
clksleep(10)
#self.debug.wr(4)
while polyphony.is_worker_running():
data16 = self.read_spi_data16()
print(data16)
self._wait()
#while is_worker_running():
# debug_v = 7 ^ debug_v
# self.led(1)
# self._wait()
# self.led(0)
# self._wait()
def _wait(self):
INTERVAL = 20000000
for i in range(INTERVAL):
pass
def debug_out(self, debug_v: uint8):
self.debug.wr(3)
self._wait()
for i in range(4):
debug_v0 = (debug_v >> ((3 - i) * 2)) & 0x3
if ((i & 1) == 0):
debug_v0 |= 4
self.debug.wr(debug_v0)
self._wait()
self.debug.wr(7)
self._wait()
self.debug.wr(0)
self._wait()
def rgb_out(self, n, v0: uint3, v1: uint3):
self.debug.wr(v0)
self._wait()
self.debug.wr(v1)
self._wait()
def debug_out0(self, debug_v: uint8):
self.rgb_out(20, 7, 0)
for i in range(4):
debug_v0 = (debug_v >> i) & 0x3
debug_v1 = debug_v0
if ((i & 1) == 0):
debug_v1 |= 4
self.rgb_out(10, debug_v0, debug_v1)
self.rgb_out(30, 7, 5)
self.debug.wr(0)
class spi_lis3dh:
def __init__(self):
self.sclk = Port(bit, 'out')
self.mosi = Port(bit, 'out')
self.miso = Port(bit, 'in')
self.cs_n = Port(bit, 'out', init=1)
self.x_led = Port(bit, 'out')
self.y_led = Port(bit, 'out')
self.z_led = Port(bit, 'out')
self.data24 = Port(uint24, 'out', protocol='ready_valid')
self.append_worker(self.worker)
def set_addr(self, rw, ms, addr):
clksleep(1)
self.sclk.wr(0)
self.mosi.wr(rw)
clksleep(2)
self.sclk.wr(1)
clksleep(2)
self.sclk.wr(0)
self.mosi.wr(ms)
clksleep(2)
self.sclk.wr(1)
clksleep(2)
self.sclk.wr(0)
for i in range(6):
bit1 = (addr >> (5 - i)) & 1
self.mosi.wr(bit1)
clksleep(1)
self.sclk.wr(1)
clksleep(1)
self.sclk.wr(0)
clksleep(1)
def read_data(self, addr):
self.cs_n.wr(0)
self.sclk.wr(0)
clksleep(1)
self.set_addr(1, 0, addr)
data = 0
for i in range(8):
data <<= 1
clksleep(1)
self.sclk.wr(1)
clksleep(1)
bit1 = self.miso.rd() & 1
clkfence()
self.sclk.wr(0)
data |= bit1
clksleep(1)
self.cs_n.wr(1)
return data
def write_data(self, addr, data):
self.cs_n.wr(0)
self.sclk.wr(0)
clksleep(1)
self.set_addr(0, 0, addr)
for i in range(8):
bit1 = (data >> (7 - i)) & 1
self.mosi.wr(bit1)
clksleep(1)
self.sclk.wr(1)
clksleep(1)
self.sclk.wr(0)
clksleep(2)
self.cs_n.wr(1)
self.mosi.wr(0)
return data
def worker(self):
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
self.write_data(0x20, 0x7F)
while polyphony.is_worker_running():
clksleep(20)
self.write_data(0x20, 0x7F)
clksleep(10)
data_who_am_i = self.read_data(0x0F)
clksleep(10)
data_x_l = self.read_data(0x29)
clksleep(10)
data_y_l = self.read_data(0x2B)
clksleep(10)
data_z_l = self.read_data(0x2D)
clksleep(10)
self.x_led.wr(1 if data_x_l > 0x30 else 0)
self.y_led.wr(1 if data_y_l > 0x30 else 0)
self.z_led.wr(1 if data_z_l > 0x30 else 0)
data_xyz = (data_x_l << 16) | (data_y_l << 8) | data_z_l
self.data24.wr(data_xyz)
