def tx_char(self, char_c):
wait_value(0, self.tx_busy)
self.tx_data.wr(char_c)
self.tx_start.wr(1)
clkfence()
wait_value(1, self.tx_busy)
self.tx_start.wr(0)
def worker(self):
wait_value(True, self.start)
self.sub1.i.wr(10)
self.sub2.i.wr(20)
clksleep(10)
result1 = self.sub1.o.rd() == 20
result2 = self.sub2.o.rd() == 60
self.result.wr(result1 and result2)
def test(m):
m.inf.a.i.wr(100)
wait_value(200, m.inf.a.o)
assert m.inf.a.o.rd() == 200
m.inf.b.i.wr(101)
wait_value(201, m.inf.b.o)
assert m.inf.b.o.rd() == 201
def test(m):
m.inf.i0.wr(1)
wait_value(1, m.inf.o0)
assert m.inf.o0.rd() == 1
m.inf.i1.wr(1)
wait_value(1, m.inf.o1)
assert m.inf.o1.rd() == 1
def write_data(self, addr: uint8, data: uint8):
self.rw(1)
self.addr(addr)
self.data_out(data)
clkfence()
self.stb(1)
clkfence()
wait_value(1, self.ack)
clkfence()
self.stb(0)
def main(self):
self.start(True)
while is_worker_running():
self.out_valid(False)
wait_value(True, self.in_valid)
i = self.in0()
self.out0(i * i)
clkfence()
self.out_valid(True)
break
def test(p05):
wait_value(True, p05.start)
p05.in0(2)
p05.in_valid(True)
print('wait out_valid')
wait_value(True, p05.out_valid)
assert p05.out0() == 4
clkfence()
print(p05.out0())
def read_data(self, addr: uint8):
data: uint8 = 0
self.rw(0)
self.addr(addr)
clkfence()
self.stb(1)
clkfence()
wait_value(1, self.ack)
data = self.data_in.rd()
clkfence()
self.stb(0)
return data
def test(p01):
# wait to ensure the test starts after the worker is running
wait_value(1, p01.start)
p01.in0(2)
p01.in_valid(1)
print('wait out_valid')
wait_value(1, p01.out_valid)
assert p01.out0() == 4
clkfence()
print(p01.out0())
def main(self):
self.start(1)
while is_worker_running():
self.out_valid(0)
# We have to wait the input data ...
wait_value(1, self.in_valid)
i = self.in0()
self.out0(i * i)
# clkfence() function guarantees that the writing to out_valid is executed in a next cycle
clkfence()
self.out_valid(1)
break
def test(spi_master):
for i in range(7):
wait_value(1, spi_master.sclk)
f = 0
for i in range(8):
wait_value(0, spi_master.sclk)
clkfence()
spi_master.miso.wr(f)
f = 1 - f
clksleep(1)
spi_master.miso.wr(0)
data = spi_master.data8.rd()
print("data0:", data)
def test(m):
m.i0.wr(1)
m.i1.wr(1)
m.i2.wr(1)
m.i3.wr(1)
m.i4.wr(1)
m.i5.wr(1)
m.i6.wr(1)
m.i7.wr(1)
m.i8.wr(1)
m.i9.wr(1)
wait_value(1, m.o0, m.o1, m.o2, m.o3, m.o4, m.o5, m.o6, m.o7, m.o8, m.o9)
assert m.o0.rd() == 1
assert m.o1.rd() == 1
assert m.o2.rd() == 1
assert m.o3.rd() == 1
assert m.o4.rd() == 1
assert m.o5.rd() == 1
assert m.o6.rd() == 1
assert m.o7.rd() == 1
assert m.o8.rd() == 1
assert m.o9.rd() == 1
def worker_a(self, name, i, o):
wait_value(100, i)
print('worker', name, i.rd())
o.wr(200)
def worker(self, name, i, o):
wait_value(1, i)
print('worker', name, i.rd())
o.wr(1)
def rx_char(self):
wait_value(1, self.rx_ready)
data: bit8 = self.rx_data.rd()
return data
def flush_tx(self):
wait_value(0, self.tx_busy)
def worker1(self, name, inf):
wait_value(self.param, inf.i1)
print('worker', name, inf.i1.rd())
inf.o1.wr(1)
def worker0(self, name, inf):
wait_value(self.param, inf.i0)
print('worker', name, inf.i0.rd())
inf.o0.wr(1)
def worker_b(self, name, i, o):
wait_value(101, i)
print('worker', name, i.rd())
o.wr(201)
def worker(self):
self.sbus_reset.wr(1)
clksleep(8)
self.sbus_reset.wr(0)
self.sbus_ipload(1)
self.debug.wr(4)
self._wait()
wait_value(1, self.sbus_ipdone)
self.sbus_ipload(0)
self.debug.wr(0)
clksleep(8)
self.write_data(0x07, 0x18)
self.write_data(0x0F, 2)
self.write_data(0x09, 0x80)
self.write_data(0x0A, 0xC0)
self.write_data(0x0B, 0x02)
self.write_data(0x0A, 0xC0)
self.write_data(0x0D, 0x35)
self.debug.wr(4)
irq_status = 0
while True:
irq_status = self.read_data(0x06)
irq_trdy = (irq_status >> 4) & 1
if irq_trdy == 1:
self.write_data(0x06, 0x10)
break
#self.debug.wr((irq_status >> 3) & 3)
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
if irq_rrdy == 1:
self.write_data(0x06, irq_status)
break
# self.write_data(0x0D, 0x5A)
# self.debug.wr((irq_status >> 3) & 3)
# #self.debug.wr(1)
#
# while True:
# irq_status = self.read_data(0x06)
# irq_trdy = (irq_status >> 4) & 1
# if irq_trdy == 1 :
# self.write_data(0x06, 0x10)
# #break
# irq_rrdy = (irq_status >> 3) & 1
# if irq_rrdy == 1 :
# self.write_data(0x06, 0x08)
# break
#
# self.debug.wr(1)
#self._wait()
#while True:
# irq_status = self.read_data(0x06)
# if irq_status == 0 :
# break
# self._wait()
# self.write_data(0x06, irq_status)
# self._wait()
#self.debug.wr((irq_status >> 3) & 2)
#self._wait()
self.write_data(0x0A, 0x80)
#----------------------------------------------------
self.write_data(0x0A, 0xC0)
self.write_data(0x0D, 0x12)
self.debug.wr(7)
irq_status = 0
while True:
irq_status = self.read_data(0x06)
irq_trdy = (irq_status >> 4) & 1
if irq_trdy == 1:
self.write_data(0x0D, 0xAA)
self.write_data(0x06, 0x10)
break
#self.debug.wr((irq_status >> 3) & 2)
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
if irq_rrdy == 1:
self.write_data(0x06, 0x08)
break
#self.debug.wr((irq_status >> 3) & 2)
while True:
irq_status = self.read_data(0x06)
irq_rrdy = (irq_status >> 3) & 1
if irq_rrdy == 1:
self.write_data(0x06, 0x08)
break
self.write_data(0x0A, 0x80)
clkfence()
clksleep(10)
#self.debug.wr(4)
while polyphony.is_worker_running():
data16 = self.read_spi_data16()
print(data16)
self._wait()
