def get_vhdl_port_list(vhdl_file):
# Clean up to make processing easier
vhdl_file = utils.strip_comments(vhdl_file)
vhdl_file = vhdl_file.replace('\n', ' ')
vhdl_file = vhdl_file.replace('\t', ' ')
vhdl_file = vhdl_file.lower()
# Get the generic's default
generics = re.findall("generic\W*\((.+?)\);", vhdl_file)
ports = re.findall("port\W*\((.+?)\)\W+end.*;", vhdl_file)
ports = ports[0]
# Process the Generics
for generic_line in generics[0].split(';'):
generic_result = re.search("(.*)\W*:\W*(.*)\w*:=\W*(.)", generic_line)
generic_name = generic_result.group(1).strip()
generic_value = generic_result.group(3)
ports = ports.replace(generic_name, generic_value)
# Process the Ports
module_port_list = []
for port_line in ports.split(';'):
port = hdl_port.Port("Unknown")
ports_details = re.split(', |: |\W+', port_line)
port.size = utils.range_to_num_bits(ports_details[-1])
port.direction = ports_details[-2]
for port_name in ports_details[:-2]:
port.name = port_name
module_port_list.append(port)
port = hdl_port.Port("Unknown")
return module_port_list
def _parse_verilog_port_list(portlist_str):
port_list = []
port = hdl_port.Port("unknown")
# Remove unneeded code.
portlist_str = re.sub("task.*endtask",
"",
portlist_str,
flags=re.DOTALL | re.MULTILINE)
portlist_str = re.sub("function.*endfunction",
"",
portlist_str,
flags=re.DOTALL | re.MULTILINE)
portlist_str = re.sub("\[\s*",
"[",
portlist_str,
flags=re.DOTALL | re.MULTILINE)
portlist_str = re.sub("\s*:\s*",
":",
portlist_str,
flags=re.DOTALL | re.MULTILINE)
portlist_str = re.sub("\s*\]",
"]",
portlist_str,
flags=re.DOTALL | re.MULTILINE)
for token in filter(None, re.split('[,\t\n ]+', portlist_str)):
token = token.strip()
if token in _keyword_port:
port = hdl_port.Port("unknown")
port.size = 1
port.direction = token
elif (token == "") or (port is None):
pass
elif token[0] == '[': # This is a size description
port.size = utils.range_to_num_bits(token)
elif token in _keyword_type:
pass
elif token in _keyword_logic: # We're into the logic description, doneski!
return port_list
elif token == ';': # Last character is a ';'
port = None
else:
if token[-1] == ';':
port.name = token[:-1]
port_list.append(port)
port = None
else:
try:
port.name = token
port_list.append(port)
port = hdl_port.Port("unknown", port.direction,
port.comment, port.size, port.default)
except KeyError:
print "Error:",
print port
print token
return port_list
def test_custom_weather(self):
testportNone = port.Port(None, None, None, None, None, None)
testportCity = port.Port(None, "Dordrecht", None, None, None, None)
self.assertFalse(testportNone.check_custom_weather(500, 2))
self.assertFalse(testportNone.check_custom_weather(5000, 10))
self.assertFalse(testportNone.check_custom_weather(500, 10))
self.assertIsNone(testportNone.check_custom_weather(None, None))
self.assertIsNone(testportNone.check_custom_weather(None, 10))
self.assertIsNone(testportNone.check_custom_weather(5000, None))
self.assertIsNone(testportNone.check_custom_weather(5000, 2))
self.assertTrue(testportCity.check_custom_weather(5000, 2))
s1 = switch.Switch("s1")
topo.addSwitch(s1)
s2 = switch.Switch("s2")
topo.addSwitch(s2)
s3 = switch.Switch("s3")
topo.addSwitch(s3)
#s3.chassi=100
s4 = switch.Switch("s4")
topo.addSwitch(s4)
h1 = host.Host('h1')
h1.addPort(port.Port('AA:AA:AA:CC:CC:CC'))
h1.addPort(port.Port('AA:AA:AA:AC:CC:CC'))
h2 = host.Host('h2')
h2.addPort(port.Port('AA:AA:AA:CC:CC:CD'))
h3 = host.Host('h3')
h3.addPort(port.Port('AA:AA:AA:CC:CC:CE'))
h4 = host.Host('h4')
h4.addPort(port.Port('AA:AA:AA:CC:CC:CF'))
s1.addConnection(4, s3, 1, bandwidth=topology._10M) # Link de 1 Gbps
s3.addConnection(1, s1, 4, bandwidth=topology._10M) # Link de 1 Gbps
def __init__(
self,
pol,
src='any',
dst='any',
sport='any',
dport='any',
proto='any',
):
self.pol_obj = pol
self.proto = proto
# validate source port
if sport == 'any':
self.sport = sport
else:
self.sport = port.Port(sport)
# validate destination port
if dport == 'any':
self.dport = dport
else:
self.dport = port.Port(dport)
# validate source address
if src == 'any':
self.src = src
else:
try:
self.src = nacaddr.IP(src)
except ValueError:
raise AddressError('bad source address: %s\n' % src)
# validate destination address
if dst == 'any':
self.dst = dst
else:
try:
self.dst = nacaddr.IP(dst)
except ValueError:
raise AddressError('bad destination address: %s\n' % dst)
if type(self.pol_obj) is not policy.Policy:
raise BadPolicy('Policy object is not valid.')
self.matches = []
self.exact_matches = []
for header, terms in self.pol_obj.filters:
filtername = header.target[0].options[0]
for term in terms:
possible = []
logging.debug('checking term: %s', term.name)
if not self._AddrInside(self.src, term.source_address):
logging.debug('srcaddr does not match')
continue
logging.debug('srcaddr matches: %s', self.src)
if not self._AddrInside(self.dst, term.destination_address):
logging.debug('dstaddr does not match')
continue
logging.debug('dstaddr matches: %s', self.dst)
if (self.sport != 'any' and term.source_port and
not self._PortInside(self.sport, term.source_port)):
logging.debug('sport does not match')
continue
logging.debug('sport matches: %s', self.sport)
if (self.dport != 'any'
and term.destination_port and not self._PortInside(
self.dport, term.destination_port)):
logging.debug('dport does not match')
continue
logging.debug('dport matches: %s', self.dport)
if (self.proto != 'any' and term.protocol
and self.proto not in term.protocol):
logging.debug('proto does not match')
continue
logging.debug('proto matches: %s', self.proto)
if term.protocol_except and self.proto in term.protocol_except:
logging.debug('protocol excepted by term, no match.')
continue
logging.debug('proto not excepted: %s', self.proto)
if not term.action: # avoid any verbatim
logging.debug('term had no action (verbatim?), no match.')
continue
logging.debug('term has an action')
possible = self._PossibleMatch(term)
self.matches.append(
Match(filtername, term.name, possible, term.action,
term.qos))
if possible:
logging.debug(
'term has options: %s, not treating as exact match',
possible)
continue
# if we get here then we have a match, and if the action isn't next and
# there are no possibles, then this is a "definite" match and we needn't
# look for any further matches (i.e. later terms may match, but since
# we'll never get there we shouldn't report them)
if 'next' not in term.action:
self.exact_matches.append(
Match(filtername, term.name, [], term.action,
term.qos))
break
def create_wrapper(file_list,
wrapper_name="top_level",
prefix=None,
suffix=None,
blackbox=False):
"""
Reads each of the rtl modules from file_list.
Creates a toplevel module with all the ports
Instance each sub module with the following rules of connecting pins:
1) if the pin is only an input to each sub module, it's an input from the top
2a) if the pin is output from more than one module, prepend inst and bring to top level
2b) if the pin is output from one module only, bring to top level
2c) if pin is output from one module and input to another, interconnect only.
2d) if pin is output from one module only and input to multiple subblocks, interconnect only
3) Repeat rules 1-3 are repeated with the prefix/suffix removed/added.
4) Repeat rules 1-4 with fuzzy matching
5) All other pins are brought to the top level with the same directionality
Black box modules only bring out pins but don't instance sub modules
Suffix/Prefix lists help to better match pins.
TODO: Pass a top level black box and hook subblocks into it.
TODO: Pass a translation function for known port name changes.
:param file_list: A list of tuples that contain HDL files to instance in the wrapper and instance names.
Give the same filename multiple times for multiple instances,
:param wrapper_name: The name to give the top level wrapper module
:param prefix: A list of known prefixes to help with port matching
:param suffix: A list of known suffixes to help with port matching
:param blackbox: Only instance the toplevel module without the sub-blocks.
:return: A new module with the sub-modules instanced and wired according to the rules above.
"""
log = logging.getLogger("WRAPPER")
logging.basicConfig(level=logging.DEBUG)
# Create the top level module
if os.path.exists(wrapper_name):
top_level = Module(wrapper_name)
else:
top_level = Module()
top_level.module_name = os.path.split(wrapper_name)[-1].split('.')[-2]
# Add all the sub modules
for (subblock_fn, inst_name) in file_list:
top_level.add_subblock(Module(subblock_fn))
top_level.sub_blocks[-1].inst_name = inst_name
for subblk in top_level.sub_blocks: # Connect each block
for blk_port in subblk: # Connect each port on the block
# Now check for internal connections or if we need to add to the toplevel.
num_outputs = output_from_all_blks(blk_port.name,
top_level.sub_blocks, prefix,
suffix)
num_inputs = input_to_all_blks(blk_port.name, top_level.sub_blocks,
prefix, suffix)
if blk_port.direction == "input":
if num_outputs == 0:
top_level.add_port_list([blk_port])
if num_inputs > 1:
log.warn(
"Input : {}:{} - From top - Single input from top to multiple instances"
.format(subblk.inst_name, blk_port.name))
else:
log.debug("Input : {}:{} - From top".format(
subblk.inst_name, blk_port.name))
elif num_outputs == 1:
log.debug("Input : {}:{} - Internal connection".format(
subblk.inst_name, blk_port.name))
blk_port.connection = remove_prefix(
remove_suffix(blk_port.name, suffix), prefix)
else:
log.warn("Input : {}:{} - Multiple drivers".format(
subblk.inst_name, blk_port.name))
elif blk_port.direction == "output":
if num_outputs == 1:
# Straight point to point internal connection or...
# One output connected to multiple inputs for internal blocks else...
# Not an internal connection, bring to the top level.
if num_inputs > 0:
log.debug(
"Output : {}:{} - Internal Single output to one or more inputs"
.format(subblk.inst_name, blk_port.name))
blk_port.connection = remove_prefix(
remove_suffix(blk_port.name, suffix), prefix)
top_level.add_wire(
rtl_port.Port(blk_port.connection, "output", "",
blk_port.size))
else:
log.debug("Output : {}:{} - To top".format(
subblk.inst_name, blk_port.name))
top_level.add_port_list([blk_port])
else:
# N outputs connected to N inputs:
if num_inputs == 0:
log.debug(
"Output : {}:{} - Multiple To top, prefix instance"
.format(subblk.inst_name, blk_port.name))
blk_port.connection = subblk.inst_name + "_" + blk_port.name
toplevelport = rtl_port.Port(blk_port.connection,
"output",
blk_port.comment,
blk_port.size)
top_level.add_port_list([toplevelport])
elif num_outputs == num_inputs:
log.warn(
"TODO: Multiple outputs connected to N input(s)")
blk_port.connection = "/* Unconnected */"
else:
log.warn(
"TODO: Multiple outputs connected to one or more input(s) need to be concatenated"
)
blk_port.connection = "/* Unconnected */"
else:
log.error("Can only handle input/output type ports")
return top_level.export_rtl()
topo = topology.Topology()
central=switch.Switch("central")
topo.addSwitch(central)
for z in range(10):
s1 = switch.Switch("s1")
topo.addSwitch(s1)
central.addConnection(z,s1,101,topology._100M)
s2 = switch.Switch("s2")
topo.addSwitch(s2)
central.addConnection(100 + z,s2,101,topology._100M)
for i in range(100):
h=host.Host("h"+str(i))
h.addPort(port.Port('AA:AA:AA:CC:CC:CF'))
s1.addConnection(i,h,h.ports[0],topology._100M)
for i in range(100):
h=host.Host("h"+str(i))
h.addPort(port.Port('AA:AA:AA:CC:CC:CF'))
s2.addConnection(i,h,h.ports[0],topology._100M)
#print(topo.transferTime(h1, h2, 10 * 1024 * 1024), 'seconds')
#p = topo.findpaths(h1,h2,topology._1G)
#print(str(p))