def testSimplePortListAsString(self):
self.mp.inputs = [IO('input', 'a'), IO('input', 'b')]
self.mp.outputs = [IO('output', 'c')]
_expect = ' input a;\n'
_expect += ' input b;\n'
_expect += ' output c;\n'
self.assertEqual(self.mp.modulePortsAsString(), _expect)
def testMultiPort(self):
p = self.mp.parsePorts(
self.type, self.changePortType(self.moduleMultiplePorts))
self.assertEqual(
p,
self.changePortType(
[IO('port', 'blah'),
IO('port', 'wag'),
IO('port', 'bag')]))
def testVectorPortListAsString(self):
self.mp.inputs = [
IO('input', 'a', 'blah', 'jIb'),
IO('input', 'b', '2', '0')
]
self.mp.outputs = [IO('output', 'c', '5-1+`WHAT', '31')]
_expect = ' input [blah:jIb] a;\n'
_expect += ' input [2:0] b;\n'
_expect += ' output [5-1+`WHAT:31] c;\n'
self.assertEqual(self.mp.modulePortsAsString(), _expect)
def testPoser1InternalInputsIgnoreClkRst(self):
self.mp.inputs = [
IO('input', 'c'),
IO('input', 'clk'),
IO('input', 'rst')
]
self.mp.setClkName('clk')
self.mp.setRstName('rst', Active.lo)
self.assertEqual(
self.mp.poserInternalInputsAsString(),
' wire [poser_width_in-1:0] poser_inputs;\n assign poser_inputs = { c };\n'
)
def testIrregularlySpacedPort(self):
p = self.mp.parsePorts(
self.type, self.changePortType(self.moduleIrregularSpacing))
self.assertEqual(
p,
self.changePortType([
IO('port', 'blah', '1', '0'),
IO('port', 'wag', '1', '0'),
IO('port', 'bag', '1', '0'),
IO('port', 'dang'),
IO('port', 'biggy', 'flaGGs-54', '34'),
]))
def testPoserParams(self):
self.mp.inputs = [IO('input', 'a'), IO('input', 'b')]
self.mp.outputs = [IO('output', 'c')]
self.mp.setTied(Active.hi)
self.mp.setGridSize(2, 1)
_expect = ' parameter poser_tied = 1\'b1;\n'
_expect += ' parameter poser_width_in = 0+1+1;\n'
_expect += ' parameter poser_width_out = 0+1;\n'
_expect += ' parameter poser_grid_width = 2;\n'
_expect += ' parameter poser_grid_depth = 1;\n'
_expect += ' parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = \'{ 2\'b00 };\n'
self.assertEqual(self.mp.poserParamsAsString(), _expect)
def changePortType(self, io):
if isinstance(io, list):
l = []
for s in io:
if isinstance(s, IO):
l.append(IO(self.type, s.name, s.msb, s.lsb))
else:
l.append(re.sub('port', self.type, s))
return l
else:
return re.sub('port', self.type, io)
def testPortKeyword(self):
p = self.mp.parsePorts(self.type,
self.changePortType(self.modulePortKeyword))
self.assertEqual(p, self.changePortType([IO('port', 'wag')]))
def test1Port(self):
p = self.mp.parsePorts(self.type,
self.changePortType(self.moduleSinglePort))
self.assertEqual(p, self.changePortType([IO('port', 'blah')]))
def testPoserMultipleInternalOutputs(self):
self.mp.outputs = [IO('output', 'c'), IO('output', 'd')]
self.assertEqual(
self.mp.poserInternalOutputsAsString(),
' wire [poser_width_out-1:0] poser_outputs;\n assign { c,d } = poser_outputs;\n'
)
def testPoserMultipleInternalInputs(self):
self.mp.inputs = [IO('input', 'c'), IO('input', 'd')]
self.assertEqual(
self.mp.poserInternalInputsAsString(),
' wire [poser_width_in-1:0] poser_inputs;\n assign poser_inputs = { c,d };\n'
)
def testIOAsString(self):
self.mp.inputs = [IO('input', 'a'), IO('input', 'b')]
self.mp.outputs = [IO('output', 'c')]
self.assertEqual(self.mp.moduleIOAsString(), 'a, b, c')