def test_len(self):
for _ in range(100):
size = random.randint(-10000, 0)
with self.assertRaises(ValueError):
Memory(size)
for _ in range(100):
size = random.randint(1, 10000)
memory = Memory(size)
self.assertEqual(len(memory), size)
def setUp(self):
self.clock = Clock()
self.bus = BusLog()
self.memory = Memory(10)
for i in range(len(self.memory)):
self.memory[i] = i
self.n_gpr = 6
self.rf = RegisterFile(self.n_gpr, 'r',
init_values={'r%d' % i: i for i in range(self.n_gpr)})
iu1 = IntegerUnit(self.bus)
iu2 = IntegerUnit(self.bus)
iu3 = IntegerUnit(self.bus)
rs = ReservationStation()
rs.register(iu1)
rs.register(iu2)
rs.register(iu3)
lsq = LoadStoreQueue(self.memory, self.bus)
self.rob = ReorderBuffer(self.rf, rs, lsq)
self.clock.register(self.rob)
self.clock.register(lsq)
self.clock.register(rs)
self.clock.register(iu3)
self.clock.register(iu2)
self.clock.register(iu1)
self.bus.subscribe(self.rob)
self.bus.subscribe(rs)
self.bus.subscribe(lsq)
def test_load_execute(self):
memory = Memory(64)
memory[10] = 5
load = Load('ROB1', 'ROB2')
with self.assertRaises(ValueError):
load.execute(memory)
load.receive(Result('ROB2', 10))
self.assertEqual(load.execute(memory), Result('ROB1', 5))
def test_store_execute(self):
memory = Memory(64)
memory[10] = 0
store = Store('ROB1', 'ROB3', 'ROB4')
for result in [Result('ROB3', 10), Result('ROB4', 5)]:
with self.assertRaises(ValueError):
store.execute(memory)
store.receive(result)
store.execute(memory)
self.assertEqual(memory[10], 5)
def setUp(self):
self.n_gpr_registers = 31
self.rf = RegisterFile(self.n_gpr_registers)
self.memory = Memory(128)
self.bus = BusLog()
self.log = FeedLog()
self.lsq = LoadStoreQueue(self.memory, self.bus, capacity=32)
self.generate_add = lambda cap: Add(
'r%d' % random.randint(0, cap - 1), 'r%d' % random.randint(
0, cap - 1), 'r%d' % random.randint(0, cap - 1))
def test_get_set_valid(self):
for size in [100, 4000, 10000]:
memory = Memory(size)
for i in range(100):
new_value = random.randint(-10000, 10000)
address = random.randint(0, size - 1)
# Test using addresses stored in Registers 50% of the time.
if i % 2 == 0:
address = Register(address)
memory[address] = new_value
self.assertEqual(memory[address], new_value)
def test_get_set_validate(self):
size = 200
memory = Memory(size)
for invalid_type in ['foo', None, {1}]:
with self.assertRaises(TypeError):
temp = memory[invalid_type]
with self.assertRaises(TypeError):
memory[invalid_type] = 5
for _ in range(100):
invalid_idx = random.randint(-10000, -1)
with self.assertRaises(IndexError):
temp = memory[invalid_idx]
with self.assertRaises(IndexError):
memory[invalid_idx] = 5
def setUp(self):
self.memory_uid = 0
self.memory = Memory(128)
self.reset_memory()
self.bus = BusLog()
def test_init_values(self):
size = 200
memory = Memory(size)
for i in range(size):
self.assertEqual(memory[i], None)
import random
from procsim.register_file import RegisterFile
from procsim.memory import Memory
LEN_ARRAY = 15
MEMORY = Memory(LEN_ARRAY)
for i in range(LEN_ARRAY):
MEMORY[i] = LEN_ARRAY - i
REGISTER_FILE = RegisterFile(6)
def console_output():
return 'pc: %d memory: %r' % (REGISTER_FILE['pc'], MEMORY.memory)
# r0 is zero
# r1 holds len_array - 1
# r2 holds swap flag
# r3 holds inner idx
# r4 holds arr[i]
# r5 holds arr[i + 1]
PROGRAM = [
'addi r1 r1 %d' % (LEN_ARRAY - 1),
# Reset swap flag, inner idx.
'addi r2 r0 0',
'addi r3 r0 0',
# Load next pair.
'ldr r4 r3',
'addi r3 r3 1',
import numpy as np
import matplotlib.pyplot as plt
from procsim.memory import Memory
from procsim.register_file import RegisterFile
images = np.load('programs/images.npz')
david = images['david']
(dim_y, dim_x) = david.shape
n_pixels = dim_y * dim_x
image = david.flatten()
total = 2 + n_pixels * 4
MEMORY = Memory(total)
for i in range(total):
MEMORY.memory[i] = 0
for i in range(n_pixels):
MEMORY.memory[1 + i] = int(image[i])
REGISTER_FILE = RegisterFile(31)
def console_output():
return 'pc: %2d r0: %r r1: %r r2: %r r3: %r r4: %r r5: %r r6: %r r7: %r r8: %r r17: %r r18: %r r19: %r r20: %r' % (
REGISTER_FILE['pc'], REGISTER_FILE['r0'], REGISTER_FILE['r1'],
REGISTER_FILE['r2'], REGISTER_FILE['r3'], REGISTER_FILE['r4'],
REGISTER_FILE['r5'], REGISTER_FILE['r6'], REGISTER_FILE['r7'],
REGISTER_FILE['r8'], REGISTER_FILE['r17'], REGISTER_FILE['r18'],
REGISTER_FILE['r19'], REGISTER_FILE['r20'])