def reshapedInitItems(actualCellSize, requestedCellSize, values):
"""
Convert array item size and items cnt while size of array remains unchanged
:param actualCellSize: actual size of item in array
:param requestedCellSize: requested size of item in array
:param values: input array
:return: generator of new items of specified characteristic
"""
if (actualCellSize < requestedCellSize
and requestedCellSize % actualCellSize == 0):
itemsInCell = requestedCellSize // actualCellSize
for itemsInWord in grouper(itemsInCell, values, padvalue=0):
yield int_list_to_int(itemsInWord, actualCellSize * 8)
else:
raise NotImplementedError(
f"Reshaping of array from cell size {actualCellSize:d} to {requestedCellSize:d}")
def test_single_write(self):
u = self.u
d = int_list_to_int(range(u.CACHE_LINE_SIZE), 8)
u.w._ag.data.append((1, d, mask(u.CACHE_LINE_SIZE)))
self.runSim(10 * CLK_PERIOD)
aw = u.m.aw._ag
self.assertValSequenceEqual(aw.data, [
aw.create_addr_req(addr=1 * u.CACHE_LINE_SIZE,
_len=u.BUS_WORDS_IN_CACHE_LINE - 1,
_id=0),
])
self.assertValSequenceEqual(
u.m.w._ag.data,
[(get_bit_range(d, u.DATA_WIDTH * i,
u.DATA_WIDTH), mask(u.DATA_WIDTH // 8), int(last))
for last, i in iter_with_last(range(u.BUS_WORDS_IN_CACHE_LINE))])
def test_bit_list_reversed_bits_in_bytes(self):
bits = int_to_int_list(0x010203, 1, 3 * 8)
rev_bits = bit_list_reversed_bits_in_bytes(bits)
v = int_list_to_int(rev_bits, 1)
self.assertEqual(v, 0x8040c0, f"0x{v:x} 0x8040c0")
def test_int_list_to_int(self):
self.assertEqual(int_list_to_int([0x1, 0x2, 0x3], 4), 0x321)
def build_cacheline(self, cacheline_words):
return int_list_to_int(cacheline_words, self.u.DATA_WIDTH)