def test_sample(sim_cls):
directed(
drv(t=Uint[2], seq=[1, 2]) | delay(2),
f=sample(sim_cls=sim_cls),
ref=[1, 1, 1, 2])
sim(timeout=7)
def test_hold(lang):
@gear
async def wr_sequence() -> Uint[4]:
for i in range(4):
yield i + 1
await clk()
await clk()
await clk()
raise GearDone
@gear
async def rd_sequence() -> Unit:
for i in range(4):
yield Unit()
await clk()
await clk()
raise GearDone
directed(wr_sequence(),
rd_sequence(),
f=state(hold=True),
ref=[0, 2, 3, 4],
delays=[delay(2)])
cosim('/state', 'verilator', lang=lang)
sim()
from pygears.lib import drv, check, ccat, delay from pygears.typing import Uint x = drv(t=Uint[5], seq=[10, 11, 12]) | delay(2) y = drv(t=Uint[5], seq=[20, 21, 22]) ccat(x, y) | check(ref=[(10, 20), (11, 21), (12, 22)])
from pygears.lib import sdp, check, drv, delay
from pygears.typing import Uint, Tuple
wr_addr_data = drv(t=Tuple[Uint[2], Uint[3]],
seq=[(0, 0), (1, 2), (2, 4), (3, 6)])
rd_addr = drv(t=Uint[2], seq=[0, 1, 2, 3]) | delay(1)
rd_addr \
| sdp(wr_addr_data) \
| check(ref=[0, 2, 4, 6])
from pygears.lib import drv, check, czip, delay from pygears.typing import Queue, Uint x = drv(t=Queue[Uint[5]], seq=[[10, 11, 12]]) | delay(2) y = drv(t=Queue[Uint[5]], seq=[[20, 21, 22]]) czip(x, y) | check(ref=[[(10, 20), (11, 21), (12, 22)]])