def test_complex(din_delay, dout_delay): @gear async def test(din, *, chunk_len, num_workers) -> b'din': counter = Uint[bitw(chunk_len * chunk_len)](0) chunk_pow = chunk_len * chunk_len async for arr, last_arr in din: if counter >= chunk_pow: counter = 0 if not last_arr: yield arr, last_arr counter += 1 if last_arr: if counter == chunk_pow - 1: yield arr, last_arr else: yield arr, Uint[1](0) counter += 1 while counter < chunk_pow - 1 and last_arr: yield [[0] * chunk_len] * num_workers, Uint[1](0) counter += 1 yield [[0] * chunk_len] * num_workers, Uint[1](1) t = Queue[Array[Array[Uint[4], 2], 2]] verif(drv(t=t, seq=[[((1, 2), (2, 3))] * 5]) | delay_rng(din_delay, din_delay), f=test(name='dut', chunk_len=2, num_workers=2), ref=test(chunk_len=2, num_workers=2), delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_cond_nested_loop(din_delay, dout_delay): @gear async def test(din: Queue[Bool]) -> Uint[4]: a = Uint[4](0) i = Uint[4](0) while i < 4: if i < 2: async for d in din: print(f'1: {a}') yield a a += 1 i = 2 else: async for d in din: print(f'2: {a}') yield a a += 2 i = 4 i += 1 verif(drv(t=Queue[Bool], seq=[[True] * 4, [True], [True], [True] * 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) # cosim('/dut', 'verilator', outdir='/tools/home/tmp/shedule', rebuild=True) cosim('/dut', 'verilator') sim()
def test_double_loop(din_delay, dout_delay): @gear async def test(stop: Integer) -> b'stop + stop': cnt1 = stop.dtype(0) async with stop as s: last1 = False while not last1: cnt2 = stop.dtype(0) last2 = False while not last2: yield cnt1 + cnt2 last2 = cnt2 == s cnt2 += 1 last1 = cnt1 == s cnt1 += 1 verif(drv(t=Uint[4], seq=[2, 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_directed(sim_cls, din_delay, dout_delay): dut = get_dut(dout_delay) directed(drv(t=t_din, seq=[list(range(9)), list(range(3))]) | delay_rng(din_delay, din_delay), drv(t=t_cfg, seq=[2, 3]) | delay_rng(din_delay, din_delay), f=dut(sim_cls=sim_cls), ref=[[0, 1], [2, 3], [4, 5], [6, 7], [8], [0, 1, 2]], delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_state_in_scope(din_delay, dout_delay): @gear async def test(din: Queue[Uint[4]]) -> Uint[4]: async for c, eot in din: yield c yield c verif(drv(t=Queue[Uint[4]], seq=[[2, 6, 10, 14]]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_delay(cosim_cls, din_delay, dout_delay): def bitfield(n): return [int(digit) for digit in bin(n)[2:]] seq = [bitfield(0x73), bitfield(0x00)] init = [1, 0] dut = get_decoupled_dut(dout_delay, reduce(f=lambda x, y: x ^ y)) verif(drv(t=Queue[Bool], seq=seq) | delay_rng(din_delay, din_delay), drv(t=Uint[8], seq=init), f=dut(sim_cls=cosim_cls), ref=reduce(name='ref_model', f=lambda x, y: x ^ y), delays=[delay_rng(dout_delay, dout_delay)]) sim()
def test_din_state(din_delay, dout_delay): @gear async def test(din: Uint[4]) -> Uint[4]: async with din as c: yield c async with din as c: yield c verif(drv(t=Uint[4], seq=[1, 2, 3, 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_leave_looped(din_delay, dout_delay): @gear async def test(din: Bool) -> Bool: c = Bool(True) while c: async with din as c: if c: yield 0 else: yield 1 verif(drv(t=Bool, seq=[True, False, False, True]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_optional_loop(din_delay, dout_delay): @gear async def test(din: Uint[4]) -> Uint[4]: async with din as c: if c > 1: for i in range(2): yield i else: for i in range(3): yield i verif(drv(t=Uint[4], seq=[1, 2, 3, 4, 1, 2, 3, 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_basic_loop(din_delay, dout_delay): @gear async def test(din: Bool) -> Uint[4]: a = Uint[4](0) c = True while c: async with din as c: yield a a += 1 verif(drv(t=Bool, seq=[True, False, False, True]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_loop_after_async_with(din_delay, dout_delay): @gear async def test(din: Uint[4]) -> Uint[4]: async with din as d: yield 1 d = 0 while d < 3: async with din as d: yield 0 verif(drv(t=Uint[4], seq=[1, 2, 3, 4, 1, 2, 3, 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_double_loop_seq_explicit_split(din_delay, dout_delay): @gear async def test(din: Queue[Uint[4]]) -> Uint[5]: async for d, _ in din: yield d + 1 await clk() async for d, _ in din: yield d + 2 verif(drv(t=Queue[Uint[4]], seq=[[1, 2, 3] * 2] * 2) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_optional_loop_assign(din_delay, dout_delay): @gear async def test(din: Queue[Bool]) -> Bool: flag = False async for d, eot in din: if d: flag = True yield flag verif(drv(t=Queue[Bool], seq=[[True, False, False, True]]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_cond_2state_symetric(lang, din_delay, dout_delay): @gear async def test(din: Bool) -> Bool: async with din as d: if d: yield True yield d else: yield False yield not d directed(drv(t=Bool, seq=[True, False, True, False]) | delay_rng(din_delay, din_delay), f=test, ref=[True, True, False, True, True, True, False, True], delays=[delay_rng(dout_delay, dout_delay)]) cosim('/test', 'verilator', lang=lang) sim()
def test_cond_state(din_delay, dout_delay): @gear async def test(din: Uint[4]) -> Uint[4]: async with din as c: if c < 12: yield 1 yield 2 if c > 4: yield 3 verif(drv(t=Uint[4], seq=[2, 6, 10, 14]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_qrange(din_delay, dout_delay): @gear async def test(stop: Integer) -> b'stop': cnt = stop.dtype(0) last: Bool async with stop as s: last = False while not last: last = cnt == s yield cnt cnt += 1 verif(drv(t=Uint[4], seq=[2, 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_double_loop_seq(din_delay, dout_delay): @gear async def test(din: Uint[4]) -> Uint[4]: c = Uint[4](0) while c[:1] == 0: async with din as c: yield c c = Uint[4](0) while c[:1] == 0: async with din as c: yield code(2 * c, Uint[4]) verif(drv(t=Uint[4], seq=[1, 2, 3, 4, 1, 2, 3, 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_2state(dout_delay): @gear async def test() -> Bool: yield False yield True verif(f=test(name='dut'), ref=test(), delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim(timeout=8)
def test_cond_nested_loop_multistate(din_delay, dout_delay): @gear async def test(din: Queue[Bool]) -> Uint[4]: a = Uint[4](0) while a < 4: if a < 2: async for d in din: yield a # Influences above condition, but should not make a # difference while loop is running a += 1 a += 1 verif(drv(t=Queue[Bool], seq=[[True] * 4, [True], [True], [True] * 4]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()
def test_basic(): seq = [(0, 0x1), (1, 0x2), (2, 0x4), (3, 0x3), (4, 0x6), (5, 0x5), (6, 0x7), (7, 0x0)] ref = [ [0, 3, 5, 6], [1, 3, 4, 6], [2, 4, 5, 6], ] directed(drv(t=Tuple[Uint[8], Uint[3]], seq=seq), f=dispatch(__sim__='verilator'), delays=[delay_rng(0, 3) for _ in range(3)], ref=ref) sim()
def test_complex1(din_delay, dout_delay): @gear async def test(din: Queue, is_done) -> b'(din, din)': first_elem = True for_shred = False async for m, last in din: if for_shred: yield None, None elif first_elem: async with is_done as med_found: if med_found: for_shred = True yield None, (m, last) else: first_elem = False yield (m, last), None elif not last: first_elem = False yield (m, last), None else: first_elem = True yield (m, last), None t = Queue[Uint[4], 1] verif(drv(t=t, seq=[list(range(5))] * 3) | delay_rng(din_delay, din_delay), drv(t=Bool, seq=[False, False, True]) | delay_rng(din_delay * 2, din_delay * 2), f=test(name='dut'), ref=test, delays=[ delay_rng(dout_delay, dout_delay), delay_rng(dout_delay, dout_delay) ]) cosim('/dut', 'verilator') sim()
def test_optional_loop_assign_complex(din_delay, dout_delay): @gear async def test(din: Queue) -> Uint[8]: max_el = din.dtype.data.min max_idx = Uint[8](0) cnt = Uint[8](0) async for d, eot in din: if d >= max_el: max_el = d max_idx = cnt cnt += 1 yield max_idx seq = list(range(4)) + list(range(4, 0, -1)) verif(drv(t=Queue[Uint[4]], seq=[seq, seq]) | delay_rng(din_delay, din_delay), f=test(name='dut'), ref=test, delays=[delay_rng(dout_delay, dout_delay)]) cosim('/dut', 'verilator') sim()