def frame_buffer(din: Queue[Uint['w_din'], 1],
rd_addr: Queue[Array[Tuple[Uint['w_rect'], Uint[1],
Int['w_weight']], 3],
3], rst_in: Unit, *, frame_size):
##########Parameters###################
ram_size = frame_size[0] * frame_size[1]
w_addr = math.ceil(math.log(ram_size, 2))
#######################################
rst_in | local_rst
din_i, rd_addr_sdp = alternate_queues(din, rd_addr)
rd_addr_sdp_dreg = rd_addr_sdp | dreg
cfg_rng = ccat(0, Uint[w_addr](ram_size), 1)
wr_addr = cfg_rng | rng
wr_sdp = ccat(wr_addr[0], din_i[0])
rd_data0 = sdp(wr_sdp, rd_addr_sdp[0][0][0], depth=ram_size)
rd_data1 = sdp(wr_sdp, rd_addr_sdp[0][1][0], depth=ram_size)
rd_data2 = sdp(wr_sdp, rd_addr_sdp[0][2][0], depth=ram_size)
rd_data0 = ccat(rd_data0, rd_addr_sdp_dreg[0][0][1],
rd_addr_sdp_dreg[0][0][2])
rd_data1 = ccat(rd_data1, rd_addr_sdp_dreg[0][1][1],
rd_addr_sdp_dreg[0][1][2])
rd_data2 = ccat(rd_data2, rd_addr_sdp_dreg[0][2][1],
rd_addr_sdp_dreg[0][2][2])
rd_data = ccat(rd_data0, rd_data1, rd_data2) | Array[rd_data0.dtype, 3]
dout = ccat(rd_data, rd_addr_sdp_dreg[1]) | Queue[rd_data.dtype, 3]
return dout | decouple_sp
def test_directed(sim_cls):
wr_addr_data = [(i, i * 2) for i in range(4)]
rd_addr = list(range(4))
rd_data = [i * 2 for i in range(4)]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=wr_addr_data),
drv(t=Uint[3], seq=rd_addr) | delay_rng(1, 1),
f=sdp(sim_cls=sim_cls, depth=4, latency=2),
ref=rd_data)
sim()
def test_sim_prefil(sim_cls):
rd_addr = list(range(4))
mem = {i: 2 * i for i in rd_addr}
rd_data = [mem[i] for i in rd_addr]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(sim_cls=sim_cls, depth=4, mem=mem),
ref=rd_data)
sim()
def test_directed(latency):
print(f'Latency: {latency}')
wr_addr_data = [(i, i * 2) for i in range(4)]
rd_addr = list(range(4))
rd_data = [i * 2 for i in range(4)]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=wr_addr_data),
drv(t=Uint[3], seq=rd_addr) | delay_rng(latency, latency),
f=sdp(depth=4, latency=latency),
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def test_directed_full_read(latency):
print(f'Latency: {latency}')
depth = 8
mem = list(range(depth))
rd_addr = list(range(8))
rd_data = list(range(8))
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(depth=8, latency=latency, mem=mem),
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def test_directed_dout_throtle(latency):
print(f'Latency: {latency}')
depth = 8
mem = list(range(depth))
rd_addr = list(range(8))
rd_data = list(range(8))
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(depth=8, latency=latency, mem=mem),
delays=[delay_rng(4, 4)],
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def filter(pixels: Queue[Array[Uint[8], 3]], coef: Queue[Array[Fixp, 3]], *,
window_num):
window_cnt = replicate(when(coef['eot'], window_num), 3 * 3)
mem_wr_data = czip(qcnt(coef, running=True, w_out=4, init=0),
coef) | flatten
coef_rd = qrange(window_cnt['data']) \
| flatten \
| sdp(wr_addr_data=mem_wr_data, depth=16)
pix_coef = czip(pixels, coef_rd) | reorder
res = [dot(p) for p in pix_coef]
return ccat(*res)
def filter(pixels: Queue[Uint[8]], coef: Queue[Fixp], *, window_num):
coef_t = coef.dtype.data
accum_t = Fixp[coef_t.integer + 2, coef_t.width + 2]
window_cnt = replicate(window_num, 3 * 3)
mem_wr_data = czip(qcnt(coef, running=True, w_out=4, init=0),
coef) | flatten
coef_rd = qrange(window_cnt['data']) \
| flatten \
| sdp(wr_addr_data=mem_wr_data, depth=16)
return czip(pixels, coef_rd) \
| queuemap(f=mul) \
| accum(init=accum_t(0.0), cast=saturate) \
| qround \
| saturate(t=Uint[8])
def img_ram(din: Queue[Uint['w_data'], 1],
rd_addr: Queue[Uint['w_addr'], 4],
*,
img_size=(240, 320)):
##########Parameters###################
ram_size = img_size[0] * img_size[1]
#######################################
cfg_rng = ccat(0, ram_size, 1)
wr_addr = cfg_rng | rng
din, rd_addr_sdp = alternate_queues(din, rd_addr)
wr_sdp = ccat(wr_addr[0], din[0])
rd_data = sdp(wr_sdp, rd_addr_sdp[0], depth=ram_size)
dout = ccat(rd_data, rd_addr[1] | dreg) | Queue[rd_data.dtype, 2]
return dout | dreg_sp
from pygears.lib import sdp, check, drv, delay
from pygears.typing import Uint, Tuple
wr_addr_data = drv(t=Tuple[Uint[2], Uint[3]],
seq=[(0, 0), (1, 2), (2, 4), (3, 6)])
rd_addr = drv(t=Uint[2], seq=[0, 1, 2, 3]) | delay(1)
rd_addr \
| sdp(wr_addr_data) \
| check(ref=[0, 2, 4, 6])
def test_basic(tmpdir):
sdp(Intf(Tuple[Uint[8], Uint[32]]), Intf(Uint[8]))