def generate_instr_stream(self, no_label=0): prefix = '' string = '' self.instr_string_list.clear() for i in range(len(self.instr_stream.instr_list)): if i == 0: if no_label: prefix = pkg_ins.format_string( string=' ', length=pkg_ins.LABEL_STR_LEN) else: prefix = pkg_ins.format_string( string='{}:'.format(self.label_name), length=pkg_ins.LABEL_STR_LEN) self.instr_stream.instr_list[i].has_label = 1 else: if (self.instr_stream.instr_list[i].has_label): prefix = pkg_ins.format_string( string='{}:'.format( self.instr_stream.instr_list[i].label), length=pkg_ins.LABEL_STR_LEN) else: prefix = pkg_ins.format_string( string=" ", length=pkg_ins.LABEL_STR_LEN) string = prefix + self.instr_stream.instr_list[i].convert2asm() self.instr_string_list.append(string) prefix = pkg_ins.format_string(str(i), pkg_ins.LABEL_STR_LEN)
def generate_return_routine(self, prefix): string = '' jump_instr = [riscv_instr_name_t.JALR] rand_lsb = random.randrange(0, 1) ra = vsc.rand_enum_t(riscv_reg_t) try: with vsc.randomize_with(ra): ra.not_inside(vsc.rangelist(cfg.reserved_regs)) ra != riscv_reg_t.ZERO except Exception: logging.critical("Cannot randomize ra") sys.exit(1) string = (prefix + pkg_ins.format_string("{}addi x{} x{} {}".format( ra.name, cfg.ra.name, rand_lsb))) self.instr_string_list.append(string) if (not cfg.disable_compressed_instr): jump_instr.append(riscv_instr_name_t.C_JR) if (not (riscv_reg_t.RA in {cfg.reserved_regs})): jump_instr.append(riscv_instr_name_t.C_JALR) i = random.randrange(0, len(jump_instr) - 1) if (jump_instr[i] == riscv_instr_name_t.C_JAL): string = prefix + pkg_ins.format_string("{}c.jalr x{}".format( ra.name)) elif (jump_instr[i] == riscv_instr_name_t.C_JR): string = prefix + pkg_ins.format_string("{}c.jr x{}".format( ra.name)) elif (jump_instr[i] == riscv_instr_name_t.JALR): string = prefix + pkg_ins.format_string( "{}c.jalr x{} x{} 0".format(ra.name, ra.name)) else: logging.critical("Unsupported jump_instr: %0s" % (jump_instr[i])) sys.exit(1) self.instr_string_list.append(string)
def generate_return_routine(self, prefix): string = '' jump_instr = [riscv_instr_name_t.JALR] rand_lsb = random.randrange(0, 1) ra = vsc.enum_t(riscv_reg_t) # TODO # `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(ra,!(ra inside {cfg.reserved_regs}) ra != ZERO) string = (prefix + pkg_ins.format_string("{}addi x{} x{} {}".format( ra.name, cfg.ra.name, rand_lsb))) self.instr_string_list.append(string) if (not cfg.disable_compressed_instr): jump_instr.append(riscv_instr_name_t.C_JR) if (not (riscv_reg_t.RA in {cfg.reserved_regs})): jump_instr.append(riscv_instr_name_t.C_JALR) i = random.randrange(0, len(jump_instr) - 1) if (jump_instr[i] == riscv_instr_name_t.C_JAL): string = prefix + pkg_ins.format_string("{}c.jalr x{}".format( ra.name)) elif (jump_instr[i] == riscv_instr_name_t.C_JR): string = prefix + pkg_ins.format_string("{}c.jr x{}".format( ra.name)) elif (jump_instr[i] == riscv_instr_name_t.JALR): string = prefix + pkg_ins.format_string( "{}c.jalr x{} x{} 0".format(ra.name, ra.name)) else: logging.critical("Unsupported jump_instr: %0s" % (jump_instr[i])) sys.exit(1) self.instr_string_list.append(string)
def generate_instr_stream(self, no_label=0): prefix = '' string = '' self.instr_string_list.clear() for i in range(len(self.instr_stream.instr_list)): if i == 0: if no_label: prefix = pkg_ins.format_string( string=' ', length=pkg_ins.LABEL_STR_LEN) else: prefix = pkg_ins.format_string( string='{}:'.format(self.label_name), length=pkg_ins.LABEL_STR_LEN) self.instr_stream.instr_list[i].has_label = 1 else: if self.instr_stream.instr_list[i].has_label: prefix = pkg_ins.format_string( string='{}:'.format( self.instr_stream.instr_list[i].label), length=pkg_ins.LABEL_STR_LEN) else: prefix = pkg_ins.format_string( string=" ", length=pkg_ins.LABEL_STR_LEN) string = prefix + self.instr_stream.instr_list[i].convert2asm() self.instr_string_list.append(string) if (rcs.support_pmp and not re.search("main", self.label_name)): self.instr_string_list.insert(0, ".align 2") self.insert_illegal_hint_instr() prefix = pkg_ins.format_string("{}:".format(i), pkg_ins.LABEL_STR_LEN) if not self.is_main_program: self.generate_return_routine(prefix)
def gen_ecall_handler(self, hart): string = "" string = pkg_ins.format_string(pkg_ins.get_label( "ecall_handler:", hart), pkg_ins.LABEL_STR_LEN) self.instr_stream.append(string) self.dump_perf_stats() self.gen_register_dump() string = pkg_ins.format_string(" ", pkg_ins.LABEL_STR_LEN) string = string + "j write_tohost" self.instr_stream.append(string)
def gen_pop_stack_instr(self, stack_len, saved_regs): self.stack_len = stack_len self.saved_regs = saved_regs self.init() self.gen_instr(1) self.pop_stack_instr = [0] * (self.num_of_reg_to_save + 1) for i in range(len(self.pop_stack_instr)): self.pop_stack_instr[i] = riscv_instr() for i in range(len(self.saved_regs)): if rcs.XLEN == 32: self.pop_stack_instr[i] = riscv_instr.get_instr(riscv_instr_name_t.LW) with self.pop_stack_instr[i].randomize_with(): self.pop_stack_instr[i].rd == self.saved_regs[i] self.pop_stack_instr[i].rs1 == cfg.sp self.pop_stack_instr[i].imm == 4 * (i + 1) else: self.pop_stack_instr[i] = riscv_instr.get_instr(riscv_instr_name_t.LD) with self.pop_stack_instr[i].randomize_with(): self.pop_stack_instr[i].rd == self.saved_regs[i] self.pop_stack_instr[i].rs1 == cfg.sp self.pop_stack_instr[i].imm == 8 * (i + 1) self.pop_stack_instr[i].process_load_store = 0 # addi sp,sp,imm self.pop_stack_instr[self.num_of_reg_to_save] = riscv_instr.get_instr( riscv_instr_name_t.ADDI) with self.pop_stack_instr[self.num_of_reg_to_save].randomize_with(): self.pop_stack_instr[self.num_of_reg_to_save].rd == cfg.sp self.pop_stack_instr[self.num_of_reg_to_save].rs1 == cfg.sp self.pop_stack_instr[self.num_of_reg_to_save].imm == self.stack_len self.pop_stack_instr[self.num_of_reg_to_save].imm_str = pkg_ins.format_string( '{}'.format(self.stack_len)) self.mix_instr_stream(self.pop_stack_instr) for i in range(len(self.instr_list)): self.instr_list[i].atomic = 1 self.instr_list[i].has_label = 0
def gen_pop_stack_instr(self, stack_len, saved_regs): self.stack_len = stack_len self.saved_regs = saved_regs self.init() self.gen_instr(1) self.pop_stack_instr = [None] * (self.num_of_reg_to_save + 1) for i in range(len(self.pop_stack_instr)): self.pop_stack_instr[i] = riscv_instr() for i in range(len(self.saved_regs)): if rcs.XLEN == 32: self.pop_stack_instr[i] = riscv_instr_ins.get_instr(riscv_instr_name_t.LW.name) with self.pop_stack_instr[i].randomize_with() as it: self.rd == self.saved_regs[i] self.rs1 == cfg.sp self.imm == 4 * (i + 1) else: self.pop_stack_instr[i] = riscv_instr_ins.get_instr(riscv_instr_name_t.LD.name) with self.pop_stack_instr[i].randomize_with() as it: self.rd == self.saved_regs[i] self.rs1 == cfg.sp self.imm == 8 * (i + 1) self.pop_stack_instr[i].process_load_store = 0 # addi sp,sp,imm self.pop_stack_instr[self.num_of_reg_to_save] = riscv_instr_ins.get_instr( riscv_instr_name_t.ADDI.name) ''' TODO `DV_CHECK_RANDOMIZE_WITH_FATAL(pop_stack_instr[num_of_reg_to_save], rd == cfg.sp; rs1 == cfg.sp; imm == stack_len;) ''' self.pop_stack_instr[self.num_of_reg_to_save].imm_str = pkg_ins.format_string( '{}', self.stack_len) self.mix_instr_stream(self.pop_stack_instr) for i in range(len(self.instr_list)): self.instr_list[i].atomic = 1 self.instr_list[i].has_label = 0
def convert2asm(self, prefix = ""): asm_str = pkg_ins.format_string(self.get_instr_name(), pkg_ins.MAX_INSTR_STR_LEN) # instr rd,imm asm_str = "{}{}, {}".format(asm_str, self.rd.name, self.get_imm()) if self.comment != "": asm_str = "{} #{}".format(asm_str, self.comment) return asm_str.lower()
def gen_section(self, label, instr): if(label != ""): string = pkg_ins.format_string("{}:".format(label), pkg_ins.LABEL_STR_LEN) self.instr_stream.append(string) for items in instr: string = pkg_ins.indent + items self.instr_stream.append(string) self.instr_stream.append("")
def gen_data_page(self, hart_id, pattern, is_kernel=0, amo=0): temp_data = [] self.data_page_str.clear() if is_kernel: self.mem_region_setting = cfg.s_mem_region elif amo: self.mem_region_setting = cfg.amo_region else: self.mem_region_setting = cfg.mem_region for i in range(len(self.mem_region_setting)): logging.info("Generate data section: {} size:0x{} xwr:0x{}".format( self.mem_region_setting[i].name, self.mem_region_setting[i].size_in_bytes, self.mem_region_setting[i].xwr)) if amo: if cfg.use_push_data_section: self.data_page_str.append( ".pushsection .{},\"aw\",@progbits;".format( self.mem_region_setting[i].name)) else: self.data_page_str.append( ".section .{},\"aw\",@progbits;".format( self.mem_region_setting[i].name)) self.data_page_str.append("{}:".format( self.mem_region_setting[i].name)) else: if cfg.use_push_data_section: self.data_page_str.append( ".pushsection .{},\"aw\",@progbits;".format( pkg_ins.hart_prefix(hart_id) + self.mem_region_setting[i].name)) else: self.data_page_str.append( ".section .{},\"aw\",@progbits;".format( pkg_ins.hart_prefix(hart_id) + self.mem_region_setting[i].name)) self.data_page_str.append("{}:".format( pkg_ins.hart_prefix(hart_id) + self.mem_region_setting[i].name)) page_size = self.mem_region_setting[i].size_in_bytes for i in range(0, page_size, 32): if page_size - 1 >= 32: temp_data = self.gen_data(idx=i, pattern=pattern, num_of_bytes=32, data=temp_data) else: temp_data = self.gen_data(idx=i, pattern=pattern, num_of_bytes=page_size - 1, data=temp_data) tmp_str = pkg_ins.format_string( ".word {}".format(pkg_ins.format_data(temp_data)), pkg_ins.LABEL_STR_LEN) self.data_page_str.append(tmp_str) if cfg.use_push_data_section: self.data_page_str.append(".popsection")
def gen_test_done(self): string = pkg_ins.format_string("test_done:", pkg_ins.LABEL_STR_LEN) self.instr_stream.append(string) self.instr_stream.append(pkg_ins.indent + "li gp, 1") if(cfg.bare_program_mode): self.instr_stream.append(pkg_ins.indent + "j write_tohost") else: self.instr_stream.append(pkg_ins.indent + "ecall")
def convert2asm(self, prefix=" "): asm_str = pkg_ins.format_string(string=self.get_instr_name(), length=pkg_ins.MAX_INSTR_STR_LEN) if self.format == riscv_instr_format_t.I_FORMAT: if self.category == riscv_instr_category_t.LOAD: asm_str = "{}{}, {}({})".format(asm_str, self.fd.name, self.get_imm(), self.rs1.name) elif self.instr_name.name in [ 'FMV_X_W', 'FMV_X_D', 'FCVT_W_S', 'FCVT_WU_S', 'FCVT_L_S', 'FCVT_LU_S', 'FCVT_L_D', 'FCVT_LU_D', 'FCVT_W_D', 'FCVT_WU_D' ]: asm_str = "{}{}, {}".format(asm_str, self.rd.name, self.fs1.name) elif self.instr_name.name in [ 'FMV_W_X', 'FMV_D_X', 'FCVT_S_W', 'FCVT_S_WU', 'FCVT_S_L', 'FCVT_D_L', 'FCVT_S_LU', 'FCVT_D_W', 'FCVT_D_LU', 'FCVT_D_WU' ]: asm_str = "{}{}, {}".format(asm_str, self.fd.name, self.rs1.name) else: asm_str = "{}{}, {}".format(asm_str, self.fd.name, self.fs1.name) elif self.format == riscv_instr_format_t.S_FORMAT: asm_str = "{}{}, {}({})".format(asm_str, self.fs2.name, self.get_imm(), self.rs1.name) elif self.format == riscv_instr_format_t.R_FORMAT: if self.category == riscv_instr_category_t.COMPARE: asm_str = "{}{}, {}, {}".format(asm_str, self.rd.name, self.fs1.name, self.fs2.name) elif self.instr_name.name in ['FCLASS_S', 'FCLASS_D']: asm_str = "{}{}, {}".format(asm_str, self.rd.name, self.fs1.name) else: asm_str = "{}{}, {}, {}".format(asm_str, self.fd.name, self.fs1.name, self.fs2.name) elif self.format == riscv_instr_format_t.R4_FORMAT: asm_str = "{}{}, {}, {}, {}".format(asm_str, self.fd.name, self.fs1.name, self.fs2.name, self.fs3.name) elif self.format == riscv_instr_format_t.CL_FORMAT: asm_str = "{}{}, {}({})".format(asm_str, self.fd.name, self.get_imm(), self.rs1.name) elif self.format == riscv_instr_format_t.CS_FORMAT: asm_str = "{}{}, {}({})".format(asm_str, self.fs2.name, self.get_imm(), self.rs1.name) else: logging.error("Unsupported floating point format: %0s", self.format.name) if self.comment != "": asm_str = asm_str + " #" + self.comment return asm_str.lower()
def convert2asm(self, prefix=""): asm_str = pkg_ins.format_string(string=self.get_instr_name(), length=pkg_ins.MAX_INSTR_STR_LEN) if self.category != riscv_instr_category_t.SYSTEM: if self.format in [riscv_instr_format_t.CI_FORMAT, riscv_instr_format_t.CIW_FORMAT]: if self.instr_name is riscv_instr_name_t.C_NOP: asm_str = "c.nop" elif self.instr_name is riscv_instr_name_t.C_ADDI16SP: asm_str = "{} sp, {}".format(asm_str, self.get_imm()) elif self.instr_name is riscv_instr_name_t.C_ADDI4SPN: asm_str = "{} {}, sp, {}".format(asm_str, self.rd.name, self.get_imm()) elif self.instr_name in [riscv_instr_name_t.C_LDSP, riscv_instr_name_t.C_LWSP, riscv_instr_name_t.C_LQSP]: asm_str = "{} {}, {}(sp)".format(asm_str, self.rd.name, self.get_imm()) else: asm_str = "{} {}, {}".format(asm_str, self.rd.name, self.get_imm()) elif self.format is riscv_instr_format_t.CL_FORMAT: asm_str = "{} {}, {}({})".format( asm_str, self.rd.name, self.get_imm(), self.rs1.name) elif self.format is riscv_instr_format_t.CS_FORMAT: if self.category is riscv_instr_category_t.STORE: asm_str = "{} {}, {}({})".format( asm_str, self.rs2.name, self.get_imm(), self.rs1.name) else: asm_str = "{} {}, {}".format(asm_str, self.rs1.name, self.rs2.name) elif self.format is riscv_instr_format_t.CA_FORMAT: asm_str = "{} {}, {}".format(asm_str, self.rd.name, self.rs2.name) elif self.format is riscv_instr_format_t.CB_FORMAT: asm_str = "{} {}, {}".format(asm_str, self.rs1.name, self.get_imm()) elif self.format is riscv_instr_format_t.CSS_FORMAT: if self.category is riscv_instr_category_t.STORE: asm_str = "{} {}, {}(sp)".format(asm_str, self.rs2.name, self.get_imm()) else: asm_str = "{} {}, {}".format(asm_str, self.rs2.name, self.get_imm()) elif self.format is riscv_instr_format_t.CR_FORMAT: if self.instr_name in [riscv_instr_name_t.C_JR, riscv_instr_name_t.C_JALR]: asm_str = "{} {}".format(asm_str, self.rs1.name) else: asm_str = "{} {}, {}".format(asm_str, self.rd.name, self.rs2.name) elif self.format is riscv_instr_format_t.CJ_FORMAT: asm_str = "{} {}".format(asm_str, self.get_imm()) else: logging.info("Unsupported format {}".format(self.format.name)) else: # For EBREAK,C.EBREAK, making sure pc+4 is a valid instruction boundary # This is needed to resume execution from epc+4 after ebreak handling if self.instr_name is riscv_instr_name_t.C_EBREAK: asm_str = "c.ebreak;c.nop;" if self.comment != "": asm_str = asm_str + " #" + self.comment return asm_str.lower()
def gen_init_section(self, hart): string = pkg_ins.format_string("init:", pkg_ins.LABEL_STR_LEN) self.instr_stream.append(string) if (cfg.enable_floating_point): self.init_floating_point_gpr() self.init_gpr() # Init stack pointer to point to the end of the user stack string = "{}la x{}, {}user_stack_end".format( pkg_ins.indent, cfg.sp.value, pkg_ins.hart_prefix(hart)) self.instr_stream.append(string) if (cfg.enable_vector_extension): self.init_vector_engine() self.core_is_initialized() self.gen_dummy_csr_write() if (rcs.support_pmp): string = pkg_ins.indent + "j main" self.instr_stream.append(string)
def enter_privileged_mode(self, mode, instrs): label = pkg_ins.format_string("{}init_{}:" .format(pkg_ins.hart_prefix(self.hart), mode), pkg_ins.LABEL_STR_LEN) ret_instr = ["mret"] regs = vsc.list_t(vsc.attr(riscv_privil_reg())) label = label.lower() self.setup_mmode_reg(mode, regs) if mode == "SUPERVISOR_MODE": self.setup_smode_reg(mode, regs) if mode == "USER_MODE": self.setup_umode_reg(mode, regs) if cfg.virtual_addr_translation_on: self.setup_satp(instrs) self.gen_csr_instr(regs, instrs) # Use mret/sret to switch to the target privileged mode instrs.append(ret_instr[0]) for i in range(len(instrs)): instrs[i] = pkg_ins.indent + instrs[i] instrs.insert(0, label)
def convert2asm(self, prefix = " "): asm_str_final = "" asm_str = "" asm_str = pkg_ins.format_string(self.get_instr_name(), pkg_ins.MAX_INSTR_STR_LEN) if self.format == riscv_instr_format_t.I_FORMAT: if self.instr_name in [riscv_instr_name_t.FSRI, riscv_instr_name_t.FSRIW]: # instr rd, rs1, rs3, imm asm_str_final = "{}{}, {}, {}, {}".format(asm_str, self.rd.name, self.rs1.name, self.rs3.name, self.get_imm()) elif self.format == riscv_instr_format_t.R_FORMAT: # instr rd, rs1 if not self.has_rs2: asm_str_final = "{}{}, {}".format(asm_str, self.rd.name, self.rs1.name) elif self.format == riscv_instr_format_t.R4_FORMAT: # instr rd, rs1, rs2, rs3 asm_str_final = "{}{}, {}, {}, {}".format(asm_str, self.rd.name, self.rs1.name, self.rs2.name, self.rs3.name) else: logging.info("Unsupported format {}".format(self.format)) if asm_str_final == "": return super().convert2asm(prefix) if self.comment != "": asm_str_final = asm_str_final + " #" + self.comment return asm_str_final.lower()
def convert2asm(self, prefix=" "): asm_str = pkg_ins.format_string(string=self.get_instr_name(), length=pkg_ins.MAX_INSTR_STR_LEN) if self.category != riscv_instr_category_t.SYSTEM: if self.format == riscv_instr_format_t.J_FORMAT: asm_str = '{} {}, {}'.format(asm_str, self.rd.name, self.get_imm()) elif self.format == riscv_instr_format_t.U_FORMAT: asm_str = '{} {}, {}'.format(asm_str, self.rd.name, self.get_imm()) elif self.format == riscv_instr_format_t.I_FORMAT: if self.instr_name == riscv_instr_name_t.NOP: asm_str = "nop" elif self.instr_name == riscv_instr_name_t.WFI: asm_str = "wfi" elif self.instr_name == riscv_instr_name_t.FENCE: asm_str = "fence" elif self.instr_name == riscv_instr_name_t.FENCE_I: asm_str = "fence.i" elif self.category == riscv_instr_category_t.LOAD: asm_str = '{} {}, {} ({})'.format(asm_str, self.rd.name, self.get_imm(), self.rs1.name) elif self.category == riscv_instr_category_t.CSR: asm_str = '{} {}, 0x{}, {}'.format(asm_str, self.rd.name, self.csr, self.get_imm()) else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rd.name, self.rs1.name, self.get_imm()) elif self.format == riscv_instr_format_t.S_FORMAT: if self.category == riscv_instr_category_t.STORE: asm_str = '{} {}, {} ({})'.format(asm_str, self.rs2.name, self.get_imm(), self.rs1.name) else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rs1.name, self.rs2.name, self.get_imm()) elif self.format == riscv_instr_format_t.B_FORMAT: if self.category == riscv_instr_category_t.STORE: asm_str = '{} {}, {} ({})'.format(asm_str, self.rs2.name, self.get_imm(), self.rs1.name) else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rs1.name, self.rs2.name, self.get_imm()) elif self.format == riscv_instr_format_t.R_FORMAT: if self.category == riscv_instr_category_t.CSR: asm_str = '{} {}, 0x{}, {}'.format(asm_str, self.rd.name, self.csr, self.rs1.name) elif self.instr_name == riscv_instr_name_t.SFENCE_VMA: asm_str = "sfence.vma x0, x0" else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rd.name, self.rs1.name, self.rs2.name) else: asm_str = 'Fatal_unsupported_format: {} {}'.format( self.format.name, self.instr_name.name) else: if self.instr_name == riscv_instr_name_t.EBREAK: asm_str = ".4byte 0x00100073 # ebreak" if self.comment != "": asm_str = asm_str + " #" + self.comment return asm_str.lower()
def convert2string(self): return pkg_ins.format_string("{} bit_width:{} val:{} type:{}".format( self, self.bit_width, hex(self.val), self.access_type))
def convert2asm(self, prefix=" "): asm_str = pkg_ins.format_string(string=self.get_instr_name(), length=pkg_ins.MAX_INSTR_STR_LEN) if (self.category.name != "SYSTEM"): if self.format.name == "J_FORMAT": asm_str = '{} {}, {}'.format(asm_str, self.rd.name, self.get_imm()) elif self.format.name == "U_FORMAT": asm_str = '{} {}, {}'.format(asm_str, self.rd.name, self.get_imm()) elif self.format.name == "I_FORMAT": if (self.instr_name == "NOP"): asm_str = "nop" elif (self.instr_name == "WFI"): asm_str = "wfi" elif (self.instr_name == "FENCE"): asm_str = "fence" elif (self.instr_name == "FENCE_I"): asm_str = "fence.i" elif (self.category.name == "LOAD"): asm_str = '{} {}, {} ({})'.format(asm_str, self.rd.name, self.get_imm(), self.rs1.name) elif (self.category.name == "CSR"): asm_str = '{} {}, 0x{}, {}'.format(asm_str, self.rd.name, self.csr, self.get_imm()) else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rd.name, self.rs1.name, self.get_imm()) elif self.format.name == "S_FORMAT": if (self.category.name == "STORE"): asm_str = '{} {}, {} ({})'.format(asm_str, self.rs2.name, self.get_imm(), self.rs1.name) else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rs1.name, self.rs2.name, self.get_imm()) elif self.format.name == "B_FORMAT": if (self.category.name == "STORE"): asm_str = '{} {}, {} ({})'.format(asm_str, self.rs2.name, self.get_imm(), self.rs1.name) else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rs1.name, self.rs2.name, self.get_imm()) elif self.format.name == "R_FORMAT": if (self.category.name == "CSR"): asm_str = '{} {}, 0x{}, {}'.format(asm_str, self.rd.name, self.csr, self.rs1.name) elif (self.instr_name == "SFENCE_VMA"): asm_str = "sfence.vma x0, x0" else: asm_str = '{} {}, {}, {}'.format(asm_str, self.rd.name, self.rs1.name, self.rs2.name) else: asm_str = 'Fatal_unsupported_format: {} {}'.format( self.format.name, self.instr_name) else: if (self.instr_name == "EBREAK"): asm_str = ".4byte 0x00100073 # ebreak" if (self.comment != ""): asm_str = asm_str + " #" + self.comment return asm_str.lower()
def post_randomize(self): for i in range(len(self.loop_cnt_reg)): self.reserved_rd.append(self.loop_cnt_reg[i]) for i in range(len(self.loop_limit_reg)): self.reserved_rd.append(self.loop_limit_reg[i]) # Generate instructions that mixed with the loop instructions self.initialize_instr_list(self.num_of_instr_in_loop) self.gen_instr(1) # Randomize the key loop instructions self.loop_init_instr = [0] * 2 * self.num_of_nested_loop self.loop_update_instr = [0] * self.num_of_nested_loop self.loop_branch_instr = [0] * self.num_of_nested_loop self.loop_branch_target_instr = [0] * self.num_of_nested_loop for i in range(self.num_of_nested_loop): # Instruction to init the loop counter try: self.loop_init_instr.insert(2 * i, riscv_instr.get_rand_instr()) # TODO '''self.loop_update_instr[i] = riscv_instr.get_rand_instr( include_instr = [riscv_instr_name_t.ADDI])''' # Removed include_instr ADDI for now to avoid unrecognized colon with self.loop_init_instr[2 * i].randomize_with(): self.loop_init_instr[2 * i].rd == self.loop_cnt_reg[i] self.loop_init_instr[2 * i].rs1 == riscv_reg_t.ZERO self.loop_init_instr[2 * i].imm == self.loop_init_val[i] self.loop_init_instr[2 * i].comment = \ pkg_ins.format_string("init loop {} counter".format(i)) except Exception: logging.critical("Cannot randomize loop init1 instruction") sys.exit(1) # Instruction to init loop limit try: self.loop_init_instr[2 * i + 1] = riscv_instr.get_rand_instr() # TODO '''self.loop_update_instr[i] = riscv_instr.get_rand_instr( include_instr = [riscv_instr_name_t.ADDI])''' # Removed include_instr ADDI for now to avoid unrecognized colon with self.loop_init_instr[2 * i + 1].randomize_with(): self.loop_init_instr[2 * i + 1].rd == self.loop_limit_reg[i] self.loop_init_instr[2 * i + 1].rs1 == riscv_reg_t.ZERO self.loop_init_instr[2 * i + 1].imm == self.loop_limit_val[i] self.loop_init_instr[2 * i + 1].comment = \ pkg_ins.format_string("init loop {} limit".format(i)) except Exception: logging.critical("Cannot randomize loop init2 instruction") sys.exit(1) # Branch target instruction, can be anything self.loop_branch_target_instr[i] = riscv_instr.get_rand_instr( include_category=[ riscv_instr_category_t.ARITHMETIC.name, riscv_instr_category_t.LOGICAL.name, riscv_instr_category_t.COMPARE.name ], exclude_instr=[riscv_instr_name_t.C_ADDI16SP]) try: with self.loop_branch_target_instr[i].randomize_with(): with vsc.if_then(self.loop_branch_target_instr[i].format == riscv_instr_format_t.CB_FORMAT): self.loop_branch_target_instr[i].rs1.not_inside( vsc.rangelist(self.reserved_rd)) self.loop_branch_target_instr[i].rs1.not_inside( vsc.rangelist(cfg.reserved_regs)) with vsc.if_then( self.loop_branch_target_instr[i].has_rd == 1): self.loop_branch_target_instr[i].rd.not_inside( vsc.rangelist(self.reserved_rd)) self.loop_branch_target_instr[i].rd.not_inside( vsc.rangelist(cfg.reserved_regs)) except Exception: logging.critical("Cannot randomize branch target instruction") sys.exit(1) self.loop_branch_target_instr[i].label = pkg_ins.format_string( "{}_{}_t".format(self.label, i)) # Instruction to update loop counter self.loop_update_instr[i] = riscv_instr.get_rand_instr() # TODO '''self.loop_update_instr[i] = riscv_instr.get_rand_instr( include_instr = [riscv_instr_name_t.ADDI])''' # Removing include_instr ADDI for now to avoid unrecognized colon # Commenting for now due to key error '''with self.loop_update_instr[i].randomize_with(): self.loop_update_instr[i].rd == self.loop_cnt_reg[i] self.loop_update_instr[i].rs1 == self.loop_cnt_reg[i] self.loop_update_instr[i].imm == self.loop_step_val[i]''' self.loop_update_instr[i].comment = pkg_ins.format_string( "update loop {} counter".format(i)) # Backward branch instruction self.loop_branch_instr[i] = riscv_instr.get_rand_instr( include_instr=[self.branch_type[i]]) self.loop_branch_instr[i].randomize() with self.loop_branch_instr[i].randomize_with(): self.loop_branch_instr[i].rs1 == self.loop_cnt_reg[i] # Getting PyVSC related error # TODO '''with vsc.if_then((self.branch_type[i] != riscv_instr_name_t.C_BEQZ) or (self.branch_type[i] != riscv_instr_name_t.C_BNEZ)): self.loop_branch_instr[i].rs2 == self.loop_limit_reg[i] ''' self.loop_branch_instr[i].comment = pkg_ins.format_string( "branch for loop {}".format(i)) self.loop_branch_instr[i].imm_str = self.loop_branch_target_instr[ i].label self.loop_branch_instr[i].branch_assigned = 1 # Randomly distribute the loop instruction in the existing instruction stream self.build_loop_instr_stream() self.mix_instr_stream(self.loop_instr, 1) for i in range(len(self.instr_list)): if (self.instr_list[i].label != ""): self.instr_list[i].has_label = 1 else: self.instr_list[i].has_label = 0 self.instr_list[i].atomic = 1