def test_array_indexing(): class t7(Hardware): def __init__(self): self.a = [ Sfix(0.1, 0, -28), Sfix(0.2, 0, -28), Sfix(0.3, 0, -28), Sfix(0.4, 0, -28) ] def main(self, i): return self.a[i] x = [0, 1, 2, 3] dut = t7() sims = simulate(dut, x, simulations=SIMULATIONS) assert sims_close(sims, rtol=1e-9, atol=1e-9) # test indexing by -1 class t8(Hardware): def __init__(self): self.a = [ Sfix(0.1, 0, -28), Sfix(0.2, 0, -28), Sfix(0.3, 0, -28), Sfix(0.4, 0, -28) ] def main(self, x): return self.a[-1] x = [0, 1] dut = t8() sims = simulate(dut, x, simulations=SIMULATIONS) assert sims_close(sims, rtol=1e-9, atol=1e-9)
def test_left_index(): class t2(Hardware): def main(self, x): ret = left_index(x) return ret dut = t2() sims = simulate(dut, [0., 0.], simulations=SIMULATIONS) assert sims_close(sims, rtol=1e-9, atol=1e-9) sims = simulate(dut, [0., 0.], simulations=SIMULATIONS, input_types=[Sfix(left=4, right=-6)]) assert sims_close(sims, rtol=1e-9, atol=1e-9)
def test_rotation(): np.random.seed(123456) inputs = 0.5 * (np.random.rand(3, 128) * 2 - 1) dut = Cordic(16, CordicMode.ROTATION) sim_out = simulate(dut, *inputs) assert sims_close(sim_out, atol=1e-4)
def test_abs_basic(): inputs = [-0.25 * np.exp(0.5j), 0.123 * np.exp(0.1j)] expect = [0.25, 0.123] dut = Abs() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expect)
def test_vectoring(): np.random.seed(123456) inputs = 0.5 * (np.random.rand(3, 128) * 2 - 1) dut = Cordic(16, CordicMode.VECTORING) sim_out = simulate(dut, *inputs) assert sims_close(sim_out, rtol=1e-4, atol=1e-4)
def test_angle_basic(): inputs = [np.exp(0.5j), np.exp(0.1j)] expect = [0.5 / np.pi, 0.1 / np.pi] dut = Angle() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expect, atol=1e-4)
def test_element_with_none_bound(): class Child(Hardware): def __init__(self): self.reg = Sfix() def main(self, a): self.reg = a class DUT(Hardware): def __init__(self): self.child1 = Child() self.child2 = Child() def main(self, a): self.child1.main(a) return a dut = DUT() inp = [0.1, 0.2, 0.3] if 'PYHA_SKIP_RTL' in os.environ: pytest.skip() with patch('os._exit', MagicMock(return_value=0)): with pytest.raises(Exception): sims = simulate(dut, inp, simulations=['HARDWARE', 'RTL'])
def test_quadrant_iv(): inputs = [0.234 - 0.92j] expect = [np.abs(inputs), np.angle(inputs) / np.pi] dut = ToPolar() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expect)
def test_submodule_lists(): class T(Hardware): def __init__(self, data1, data2): self.ram = [RAM(data1), RAM(data2)] def main(self, addr, write_val): self.ram[0].delayed_write(addr, write_val) r1 = self.ram[0].delayed_read(addr) self.ram[1].delayed_write(addr, write_val) r2 = self.ram[1].delayed_read(addr) return r1, r2 class Top(Hardware): def __init__(self, data1, data2): self.submods = [T(data1, data2), T(data1, data2)] def main(self, addr, write_val): r1, r2 = self.submods[0].main(addr, write_val) r3, r4 = self.submods[1].main(addr, write_val) return r1, r2, r3, r4 N = 128 np.random.seed(0) init1 = np.random.randint(0, N, N) init2 = np.random.randint(0, N, N) dut = Top(init1, init2) addr = list(range(N)) * 2 val = list(range(N)) * 2 sims = simulate(dut, addr, val, simulations=['HARDWARE', 'RTL', 'NETLIST']) # if get_ran_gate_simulation(): # assert VHDLSimulation.last_logic_elements == 2735 # assert VHDLSimulation.last_memory_bits == 12800 assert sims_close(sims)
def test_submodule(): class T(Hardware): def __init__(self, data1): self.ram1 = RAM(data1) def main(self, addr, write_val): self.ram1.delayed_write(addr, write_val) r = self.ram1.delayed_read(addr) return r class Top(Hardware): def __init__(self, data1): self.t = T(data1) def main(self, addr, write_val): r1 = self.t.main(addr, write_val) return r1 N = 128 np.random.seed(0) init1 = np.random.randint(0, N, N) dut = Top(init1) addr = list(range(N)) * 2 val = list(range(N)) * 2 sims = simulate(dut, addr, val, simulations=['HARDWARE', 'RTL', 'NETLIST']) # if get_ran_gate_simulation(): # # handling non-zero reset is done using LUTS :( # assert VHDLSimulation.last_logic_elements == 1643 # assert VHDLSimulation.last_memory_bits == 3200 assert sims_close(sims)
def test_basic(): inputs = [0.01] * 4 expect = [np.exp(0.01j * np.pi), np.exp(0.02j * np.pi), np.exp(0.03j * np.pi), np.exp(0.04j * np.pi)] dut = NCO() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expect, rtol=1e-2, atol=1e-4)
def test_sfix_add_shift_right_resize(shift_i): right = -18 left = 0 class T10(Hardware): def main(self, x, y, i): ret = resize(x - (y >> i), size_res=x, round_style='truncate', overflow_style='saturate') return ret x = (np.random.rand(1024) * 2) - 1 y = (np.random.rand(1024) * 2) - 1 i = [shift_i] * len(x) dut = T10() sims = simulate( dut, x, y, i, simulations=SIMULATIONS, input_types=[Sfix(0, left, right), Sfix(0, left, right), int]) assert sims_close(sims, rtol=1e-9, atol=1e-9)
def test_two(): class T(Hardware): def __init__(self, data1, data2): self.ram1 = RAM(data1) self.ram2 = RAM(data2) def main(self, addr, write_val): self.ram1.delayed_write(addr, write_val) r1 = self.ram1.delayed_read(addr) self.ram2.delayed_write(addr, write_val) r2 = self.ram2.delayed_read(addr) return r1, r2 N = 128 np.random.seed(0) init1 = np.random.randint(0, N, N) init2 = np.random.randint(0, N, N) dut = T(init1, init2) addr = list(range(N)) * 2 val = list(range(N)) * 2 sims = simulate(dut, addr, val, simulations=['HARDWARE', 'RTL', 'NETLIST']) # if get_ran_gate_simulation(): # assert VHDLSimulation.last_logic_elements == 2722 # assert VHDLSimulation.last_memory_bits == 6400 assert sims_close(sims)
def test_simple(): taps = [0.01, 0.02] dut = FIR(taps) inp = [0.1, 0.2, 0.3, 0.4] sims = simulate(dut, inp) assert sims_close(sims)
def test_remez64_random_notebook(): dut = Lookup() inp = [0] * 16 sims = simulate(dut, inp, simulations=[ 'MODEL_PYHA', 'PYHA', 'RTL']) assert sims_close(sims, rtol=1e-3) # class Lookup(Hardware): # def __init__(self): # self.mem = np.random.uniform(-1, 1, 5).tolist() # self.counter = 0 # # def main(self, x): # ret = self.mem[self.counter] # # next_counter = self.counter + 1 # if next_counter >= len(self.mem): # next_counter = 0 # # self.counter = next_counter # # return ret
def test_overflow_condition(): import pytest pytest.xfail('abs would be > 1 (1.84)') inputs = [0.92j + 0.92j] expect = [np.abs(inputs), np.angle(inputs) / np.pi] dut = ToPolar() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expect)
def test_non_symmetric(): np.random.seed(0) taps = [0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07] dut = FIR(taps) inp = np.random.uniform(-1, 1, 128) sims = simulate(dut, inp) assert sims_close(sims, rtol=1e-3, atol=1e-3)
def test_remez64_random(): np.random.seed(0) taps = scipy.signal.remez(64, [0, 0.05, 0.15, 0.5], [1, 0]) dut = BasebandFilter(taps) inp = np.random.uniform(-1, 1, 512) + np.random.uniform(-1, 1, 512) * 1j sims = simulate(dut, inp) assert sims_close(sims, rtol=1e-2)
def test_angle_unit(): np.random.seed(123456) inputs = [-0.04036712646484375 - 0.03749847412109375j] expect = np.angle(inputs) / np.pi dut = Angle() sim_out = simulate(dut, inputs, simulations=['MODEL', 'HARDWARE']) sims_close(sim_out, expected=expect, rtol=1e-2)
def test_one_packet(): dut = HeaderCorrelator(header=0x8dfc, packet_len=12 * 16) inp = hex_to_bool_list('8dfc4ff97dffdb11ff438aee2524391039a4908970b91cdb') expect = [False] * len(inp) expect[15] = True sims = simulate(dut, inp) assert sims_close(sims, expect)
def test_remez128(): np.random.seed(2) taps = signal.remez(128, [0, 0.1, 0.2, 0.5], [1, 0]) dut = FIR(taps) inp = np.random.uniform(-1, 1, 128) sims = simulate(dut, inp) assert sims_close(sims, rtol=1e-3, atol=1e-3)
def test_simple_one(): dut = CRC16(init_galois=0x48f9, xor=0x1021) inp = hex_to_bool_list('8dfc4ff97dffdb11ff438aee29243910365e908970b9475e') reload = [False] * len(inp) sims = simulate(dut, inp, reload) assert sims['MODEL_PYHA'][-1] == 0 # CRC was correct assert sims_close(sims)
def test_angle_randoms(): np.random.seed(123) inputs = (np.random.rand(1024) * 2 - 1) + ((np.random.rand(1024) * 2 - 1) * 1j) inputs *= 0.25 expect = np.angle(inputs) / np.pi dut = Angle() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expected=expect, rtol=1e-1)
def test_abs_chirp(): analytic_signal, ref_abs, ref_instantaneous_phase = chirp_stimul() inputs = analytic_signal expect = ref_abs dut = Abs() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expect)
def test_angle_chirp(): analytic_signal, ref_abs, ref_instantaneous_phase = chirp_stimul() inputs = analytic_signal expect = ref_instantaneous_phase / np.pi dut = Angle() sim_out = simulate(dut, inputs) assert sims_close(sim_out, expect, atol=1e-4)
def test_remez32_random(): np.random.seed(0) taps = scipy.signal.remez(32, [0, 0.4, 0.45, 0.5], [1, 0]) dut = BasebandFilter(taps) inp = np.random.uniform(-1, 1, 512) + np.random.uniform(-1, 1, 512) * 1j inp *= 0.75 sims = simulate(dut, inp) assert sims_close(sims, rtol=1e-3)
def test_passtrough_boolean(): class T14(Hardware): def main(self, x): return x dut = T14() inp = [True, False, True, False] sims = simulate(dut, inp, simulations=SIMULATIONS) assert sims_close(sims, rtol=1e-9, atol=1e-9)
def test_sfix_bug(): """ There was Sfix None bound based bug that made only 5. output different """ np.random.seed(4) taps = [0.01, 0.02, 0.03, 0.04, 0.03, 0.02, 0.01] dut = FIR(taps) inp = [0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1] sims = simulate(dut, inp) assert sims_close(sims, rtol=1e-2)
def test_simple(): taps = [0.01, 0.02] dut = FIR(taps) inp = [0.1, 0.2, 0.3, 0.4] sims = simulate(dut, inp, simulations=['MODEL', 'MODEL_PYHA', 'PYHA', 'RTL', 'GATE']) assert sims_close(sims)
def test_all(input_power): dut = FFTPower() inp = (np.random.uniform(-1, 1, size=1280) + np.random.uniform(-1, 1, size=1280) * 1j) * input_power inp = [complex(Complex(x, 0, -17)) for x in inp] sims = simulate(dut, inp, pipeline_flush='auto', simulations=['MODEL', 'HARDWARE']) assert sims_close(sims, rtol=1e-20, atol=1e-20)