def print_hicanns_on_dnc(dnc, indent=""):
per_dnc = Coordinate.HICANNOnDNC.enum_type.size
offset = (per_dnc / 2 - 1)
h0 = Coordinate.HICANNOnDNC(Enum(0)).toHICANNOnWafer(dnc)
h1 = Coordinate.HICANNOnDNC(Enum(per_dnc / 2)).toHICANNOnWafer(dnc)
hid0 = h0.toEnum()
hid1 = h1.toEnum()
return "{}{} - {} ({} - {}, {} - {})\n".format(indent, h0, h1,
hid0, Enum(hid0.value() + offset),
hid1, Enum(hid1.value() + offset))
def hicanns_on_dnc(dnc):
per_dnc = C.HICANNOnDNC.enum_type.size
offset = (per_dnc // 2 - 1)
h0 = C.HICANNOnDNC(Enum(0)).toHICANNOnWafer(dnc)
h1 = C.HICANNOnDNC(Enum(per_dnc // 2)).toHICANNOnWafer(dnc)
top = list(range(h0.toEnum().value(), h0.toEnum().value() + offset + 1))
bot = list(range(h1.toEnum().value(), h1.toEnum().value() + offset + 1))
return top + bot
def test_FIFO_loopback(self):
loop = False
mergers = HICANN.DNCMergerLine()
mer = HICANN.DNCMerger()
for j in range(8):
if (j % 2): mer.config = HICANN.Merger.RIGHT_ONLY
else: mer.config = HICANN.Merger.LEFT_ONLY
mer.slow = False
mer.loopback = not (j % 2)
mergers[Coordinate.DNCMergerOnHICANN(j)] = mer
HICANN.set_dnc_merger(self.h, mergers)
gbit = DNC.GbitReticle()
link = HICANN.GbitLink()
for i in range(8):
if (i % 2): link.dirs[i] = HICANN.GbitLink.Direction.TO_DNC
else: link.dirs[i] = HICANN.GbitLink.Direction.TO_HICANN
gbit[self.h.to_HICANNOnDNC()] = link
HICANN.set_gbit_link(self.h, link)
DNC.set_hicann_directions(self.fpga, self.dnc, gbit)
sent_data = []
received_data = FPGA.PulseEventContainer()
sent_data.clear()
received_data.clear()
GbitLinkOnHICANN = Coordinate.GbitLinkOnHICANN
for i in range(500): #500 events, first spike getTime non-zero
sent_data.append(
FPGA.PulseEvent(
self.h.to_DNCOnFPGA(), #DNC-number (1 for vertical setup)
self.h.to_HICANNOnDNC(), #HICANN number 0
GbitLinkOnHICANN(0), #channel number 0
HICANN.L1Address(0), #neuron number 0
500 * i + 500)) #every 500 cycles
#send and receive events
received_data = FPGA.send_and_receive(
self.fpga, self.dnc, FPGA.PulseEventContainer(sent_data), loop,
100000) #0,1 seconds
for i in range(8):
link.dirs[i] = HICANN.GbitLink.Direction.OFF
for i in range(8):
gbit[Coordinate.HICANNOnDNC(Enum(i))] = link
HICANN.set_gbit_link(self.h, link)
DNC.set_hicann_directions(self.fpga, self.dnc, gbit)
HICANN.flush(self.h) #flush to hardware
print(len(sent_data), " packets sent, ", received_data.size(),
" received")
self.assertEqual(len(sent_data), received_data.size())
def dnc_loopback(self):
gbit = DNC.GbitReticle()
# no timestamp handling
# all directions set TO_HICANN, to make sure there are no spikes interfering from the HICANNs
for i in range(8):
hc = Coordinate.HICANNOnDNC(Enum(i))
gbit[hc].timestamp_enable = False
for j in range(8):
gbit[hc].dirs[j] = HICANN.GbitLink.Direction.TO_HICANN
DNC.set_hicann_directions(self.fpga, self.dnc, gbit)
loopback = DNC.Loopback()
loopback[self.h.to_HICANNOnDNC()] = True
DNC.set_loopback(self.fpga, self.dnc, loopback)
def setUp(self):
if 'nose' in list(sys.modules.keys()):
# ugly hack to support nose-based execution...
self.FPGA_IP = '0.0.0.0'
self.PMU_IP = '0.0.0.0'
self.HICANN = 0
self.DNC = 1
self.FPGA = 0
self.LOGLEVEL = 2
self.ON_WAFER = False
self.WAFER = 0
import pyhalco_hicann_v2 as Coordinate
from pyhalbe import Handle, HICANN, FPGA, Debug
# The module pyhalbe.apicheck wraps pyhalbe for hardware-less
# apichecks. It will be enabled only if the environment variable
# PYHALBE_API_CHECK is set to true. The attribute "enabled" will be set
# accordingly. KHS.
import pyhalbe_apicheck as apicheck
from pyhalco_common import Enum
highspeed = True
arq = True
hicann_num = 1
fpga_ip = Coordinate.IPv4.from_string(self.FPGA_IP)
pmu_ip = Coordinate.IPv4.from_string(self.pmu_IP)
if self.LOGLEVEL >= 0:
Debug.change_loglevel(self.LOGLEVEL)
self.dnc = Coordinate.DNCOnFPGA(Enum(self.DNC))
self.hicann = Coordinate.HICANNOnDNC(Enum(self.HICANN))
self.f = Coordinate.FPGAGlobal(Enum(self.FPGA),
Coordinate.Wafer(Enum(self.WAFER)))
self.fpga = Handle.createFPGAHw(self.f, fpga_ip, self.dnc,
self.ON_WAFER, hicann_num, pmu_ip)
self.addCleanup(Handle.freeFPGAHw, self.fpga)
self.h = self.fpga.get(self.dnc, self.hicann)
if self.ON_WAFER:
self.h0 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(0)))
self.h1 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(1)))
self.h2 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(2)))
self.h3 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(3)))
self.h4 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(4)))
self.h5 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(5)))
self.h6 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(6)))
self.h7 = self.fpga.get(self.dnc, Coordinate.HICANNOnDNC(Enum(7)))
self.apicheck = apicheck.enabled()
if apicheck.enabled(): # equals PYHALBE_API_CHECK
# With hardware access disabled pyhalbe functions return anything
# but the expected, i.e. all unittest assertions naturally fail.
# I.e. for a functional API check they have to be disabled. KHS.
apicheck.monkeyPatch(
self, 'assert'
) # disables all functions in self that start with "assert"
# ECM says: this should be part of the tests... automatic resets during construction isn't very "standalone"
# OR it is necessary and in this case it should be a member function and documented somehow.
# FPGA reset
FPGA.reset(self.fpga)
HICANN.init(self.h, False)
if self.ON_WAFER:
HICANN.init(self.h0, False)
HICANN.init(self.h1, False)
HICANN.init(self.h2, False)
HICANN.init(self.h3, False)
HICANN.init(self.h4, False)
HICANN.init(self.h5, False)
HICANN.init(self.h6, False)
HICANN.init(self.h7, False)
def test_NeuronCurrentStimHWTest(self):
fgc = HICANN.FGControl()
fg_config = HICANN.FGConfig()
for block in [Enum(0), Enum(1)]:
block = Coordinate.FGBlockOnHICANN(block)
HICANN.set_fg_config(self.h, block, fg_config)
HICANN.set_fg_values(self.h, block, fgc.getBlock(block))
# 2nd: configure the neuron
nrn = HICANN.Neuron()
#HICANN.Neuron other_nrn = HICANN.Neuron()
nrn.address(HICANN.L1Address(42))
nrn.activate_firing(True)
nrn.enable_spl1_output(True)
nrn.enable_fire_input(False)
nrn.enable_aout(True)
nrn.enable_current_input(True)
nquad = HICANN.NeuronQuad()
nquad[Coordinate.NeuronOnQuad(X(0), Y(0))] = nrn
HICANN.set_denmem_quad(self.h, Coordinate.QuadOnHICANN(0), nquad)
# NEURON CONFIG
nrn_cfg = HICANN.NeuronConfig()
nrn_cfg.bigcap.set(Coordinate.top)
HICANN.set_neuron_config(self.h, nrn_cfg)
# set ANALOG
ac = HICANN.Analog()
ac.set_membrane_top_even(Coordinate.AnalogOnHICANN(0))
HICANN.set_analog(self.h, ac)
# CURRENT STIMULUS
fg_config = HICANN.FGConfig()
fg_config.pulselength = 15
for block in [Enum(0), Enum(1)]:
block = Coordinate.FGBlockOnHICANN(block)
HICANN.set_fg_config(self.h, block, fg_config)
stimulus = HICANN.FGStimulus()
stimulus.setContinuous(True)
stimulus[:40] = [800] * 40
stimulus[40:] = [0] * (len(stimulus) - 40)
HICANN.set_current_stimulus(self.h,
Coordinate.FGBlockOnHICANN(Enum(0)),
stimulus)
# READOUT PULSES!
#configure merger tree, phase
tree = HICANN.MergerTree()
#default settings are OK
HICANN.set_merger_tree(self.h, tree)
HICANN.set_phase(self.h)
dnc_mergers = HICANN.DNCMergerLine()
for i in range(8):
# rcv from HICANN
mer = Coordinate.DNCMergerOnHICANN(i)
dnc_mergers[mer].config = HICANN.Merger.RIGHT_ONLY
dnc_mergers[mer].slow = False
dnc_mergers[mer].loopback = False
HICANN.set_dnc_merger(self.h, dnc_mergers)
# DNC and dnc_if:
gbit = Coordinate.GbitLinkOnHICANN(0)
gl = HICANN.GbitLink()
gl.dirs[gbit.value()] = HICANN.GbitLink.Direction.TO_DNC
gr = DNC.GbitReticle()
gr[self.h.to_HICANNOnDNC()] = gl
HICANN.set_gbit_link(self.h, gl)
DNC.set_hicann_directions(self.fpga, self.dnc, gr)
HICANN.flush(self.h)
rec_pulses = FPGA.receive(self.fpga, self.dnc, 10000)
# 10 ms
print(str(rec_pulses.size()) + " packets received")
self.assertGreater(rec_pulses.size(), 0)
# Check for correct addrss of spikes
for np in range(rec_pulses.size()):
pulse = rec_pulses.get(np)
self.assertEqual(HICANN.L1Address(42), pulse.getNeuronAddress())
self.assertEqual(gbit, pulse.getChannel())
self.assertEqual(self.hicann, pulse.getChipAddress())
self.assertEqual(self.dnc, pulse.getDncAddress())
#turn off links
gl.dirs[0] = HICANN.GbitLink.Direction.OFF
gr[Coordinate.HICANNOnDNC(Enum(0))] = gl
HICANN.set_gbit_link(self.h, gl)
DNC.set_hicann_directions(self.fpga, self.dnc, gr)
HICANN.flush(self.h)