def run_sim(model,
dump_vcd=None,
test_verilog=False,
line_trace=True,
max_cycles=5000):
# Setup the model
model.elaborate()
if dump_vcd:
model.config_tracing = TracingConfigs(tracing='vcd',
vcd_file_name=dump_vcd)
if test_verilog:
if not hasattr(model, 'config_verilog_import'):
model.config_verilog_import = VerilatorImportConfigs(
vl_xinit=test_verilog, )
else:
model.config_verilog_import = VerilatorImportConfigs(
vl_xinit=test_verilog, )
model.verilog_translate_import = True
model.apply(VerilogPlaceholderPass())
model = TranslationImportPass()(model)
# Create a simulator
model.apply(SimulationPass())
# Reset model
model.sim_reset(print_line_trace=line_trace)
# Run simulation
while not model.done() and model.simulated_cycles < max_cycles:
if line_trace:
model.print_line_trace()
model.tick()
# Force a test failure if we timed out
assert model.simulated_cycles < max_cycles
# Extra ticks to make VCD easier to read
model.tick()
model.tick()
model.tick()
def construct(s):
# Interface
s.minion = MinionIfcRTL(GcdUnitMsgs.req, GcdUnitMsgs.resp)
# Configurations
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=os.path.dirname(__file__) + '/GcdUnitRTL.v',
# Name of the Verilog top level module
top_module='tut4_verilog_gcd_GcdUnitRTL',
# Port name map
port_map={
'minion.req.en': 'req_en',
'minion.req.rdy': 'req_rdy',
'minion.req.msg': 'req_msg',
'minion.resp.en': 'resp_en',
'minion.resp.rdy': 'resp_rdy',
'minion.resp.msg': 'resp_msg',
},
)
s.config_verilog_import = VerilatorImportConfigs(
# Enable native Verilog line trace through Verilator
vl_line_trace=True, )
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='GcdUnitRTL',
)
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VUninit.v',
top_module='VUninit',
port_map={
"in_": "d",
"out": "q",
})
s.config_verilog_import = VerilatorImportConfigs(vl_xinit='ones', )
s.verilog_translate_import = True
def construct(s, nbits=8):
DataType = mk_bits(nbits)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.in_val = InPort()
s.in_ = [InPort(DataType) for _ in range(4)]
s.out_val = OutPort()
s.out = [OutPort(DataType) for _ in range(4)]
#---------------------------------------------------------------------
# Configurations
#---------------------------------------------------------------------
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=os.path.dirname(__file__) + '/SortUnitStructRTL.v',
# Name of the Verilog top level module
top_module='tut4_verilog_sort_SortUnitStructRTL',
# Parameters of the Verilog module
params={'p_nbits': nbits},
# Port name map
port_map={
'in_val': 'in_val',
'in_[0]': 'in0',
'in_[1]': 'in1',
'in_[2]': 'in2',
'in_[3]': 'in3',
'out_val': 'out_val',
'out[0]': 'out0',
'out[1]': 'out1',
'out[2]': 'out2',
'out[3]': 'out3',
},
)
s.config_verilog_import = VerilatorImportConfigs(
# Enable native Verilog line trace through Verilator
vl_line_trace=False, )
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=f'SortUnitStructRTL_{nbits}bit',
)
def run_sim(th, max_cycles=1000, dump_vcd=False, translation='zeros', trace=2):
# print (" -----------starting simulation----------- ")
if translation:
th.cache.verilog_translate_import = True
th.cache.config_verilog_import = VerilatorImportConfigs(
vl_xinit=translation,
vl_trace=True if dump_vcd else False,
vl_Wno_list=['UNOPTFLAT', 'WIDTH', 'UNSIGNED'],
)
th = TranslationImportPass()(th)
th.apply(SimulationPass())
th.sim_reset()
ncycles = 0
print("")
while not th.done() and ncycles < max_cycles:
th.tick()
print("{:3d}: {}".format(ncycles, th.line_trace(trace)))
ncycles += 1
# check timeout
assert ncycles < max_cycles
th.tick()
th.tick()
def run_test_vector_sim(model,
test_vectors,
dump_vcd=None,
test_verilog=False,
line_trace=True):
# First row in test vectors contains port names
if isinstance(test_vectors[0], str):
port_names = test_vectors[0].split()
else:
port_names = test_vectors[0]
# Remaining rows contain the actual test vectors
test_vectors = test_vectors[1:]
# Setup the model
model.elaborate()
if dump_vcd:
model.config_tracing = TracingConfigs(tracing='vcd',
vcd_file_name=dump_vcd)
if test_verilog:
if not hasattr(model, 'config_verilog_import'):
model.config_verilog_import = VerilatorImportConfigs(
vl_xinit=test_verilog, )
else:
model.config_verilog_import.vl_xinit = test_verilog
model.verilog_translate_import = True
model.apply(VerilogPlaceholderPass())
model = TranslationImportPass()(model)
# Create a simulator
model.apply(SimulationPass())
# Reset model
model.sim_reset(print_line_trace=line_trace)
# Run the simulation
row_num = 0
in_ids = []
out_ids = []
groups = [None] * len(port_names)
types = [None] * len(port_names)
# Preprocess default type
# Special case for lists of ports
# NOTE THAT WE ONLY SUPPORT 1D ARRAY and no interface
for i, port_full_name in enumerate(port_names):
if port_full_name[-1] == "*":
out_ids.append(i)
port_name = port_full_name[:-1]
else:
in_ids.append(i)
port_name = port_full_name
if '[' in port_name:
# Get tokens of the full name
m = re.match(r'(\w+)\[(\d+)\]', port_name)
if not m:
raise Exception(
f"Could not parse port name: {port_name}. "
f"Currently we don't support interface or high-D array.")
groups[i] = g = (True, m.group(1), int(m.group(2)))
# Get type of all the ports
t = type(getattr(model, g[1])[int(g[2])])
types[i] = None if is_bitstruct_class(t) else t
else:
groups[i] = (False, port_name)
t = type(getattr(model, port_name))
types[i] = None if is_bitstruct_class(t) else t
for row in test_vectors:
row_num += 1
# Apply test inputs
for i in in_ids:
in_value = row[i]
t = types[i]
if t:
in_value = t(in_value)
g = groups[i]
if g[0]:
getattr(model, g[1])[g[2]] = in_value
else:
setattr(model, g[1], in_value)
# Evaluate combinational concurrent blocks
model.eval_combinational()
# Display line trace output
if line_trace:
model.print_line_trace()
# Check test outputs
for i in out_ids:
ref_value = row[i]
if ref_value == '?':
continue
g = groups[i]
if g[0]:
out_value = getattr(model, g[1])[g[2]]
else:
out_value = getattr(model, g[1])
if out_value != ref_value:
error_msg = """
run_test_vector_sim received an incorrect value!
- row number : {row_number}
- port name : {port_name}
- expected value : {expected_msg}
- actual value : {actual_msg}
"""
raise RunTestVectorSimError(
error_msg.format(row_number=row_num,
port_name=port_name,
expected_msg=ref_value,
actual_msg=out_value))
# Tick the simulation
model.tick()
# Extra ticks to make VCD easier to read
model.tick()
model.tick()
model.tick()